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mc68hc08 j b 1/d rev 1 mc68hc0 8 jb 1 t echnical data hcmos m i c r o c on t r o l l er un i t m 6 8h c 08 m 6 0 8m 6 8 h c 0 8 m 8 hc 0 8 m6 8 h c

MC68HC08JB1 ? rev. 1.0 technical data motorola technical data 3 MC68HC08JB1 technical data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola, inc. is an equal opportunity/affirmative action employer. motorola and are registered trademarks of motorola, inc. digitaldna is a trademark of motorola, inc. ?motorola, inc., 2001
technical data technical data MC68HC08JB1 ? rev. 1.0 4 technical data motorola
MC68HC08JB1 ? rev. 1.0 technical data motorola list of sections 5 technical data ?MC68HC08JB1 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . .23 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . .33 section 3. random-access memory (ram) . . . . . . . . . .45 section 4. read-only memory (rom) . . . . . . . . . . . . . . .47 section 5. configuration register (config) . . . . . . . . .49 section 6. central processor unit (cpu) . . . . . . . . . . . .53 section 7. oscillator (osc) . . . . . . . . . . . . . . . . . . . . . . .71 section 8. system integration module (sim) . . . . . . . . .75 section 9. universal serial bus module (usb) . . . . . . . .95 section 10. timer interface module (tim) . . . . . . . . . . .139 section 11. input/output ports (i/o) . . . . . . . . . . . . . . .161 section 12. external interrupt (irq) . . . . . . . . . . . . . . .177 section 13. keyboard interrupt module (kbi). . . . . . . .185 section 14. computer operating properly (cop) . . . .195 section 15. low voltage inhibit (lvi) . . . . . . . . . . . . . .201 section 16. electrical specifications . . . . . . . . . . . . . . .203 section 17. mechanical specifications . . . . . . . . . . . . .211
list of sections technical data MC68HC08JB1 ? rev. 1.0 6 list of sections motorola
MC68HC08JB1 ? rev. 1.0 technical data motorola table of contents 7 technical data ?MC68HC08JB1 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.1 power supply pins (v dd , v ss ) . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.2 voltage regulator out (v reg ) . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.3 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 29 1.5.4 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.5 external interrupt pins (irq , pte4/d? . . . . . . . . . . . . . . . . 29 1.5.6 port a input/output (i/o) pins (pta7/kba7?ta0/kba0). . 29 1.5.7 port c i/o pins (ptc0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.8 port d i/o pins (ptd0/1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.9 port e i/o pins (pte4/d? pte3/d+, pte1/tch0) . . . . . . . 30 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
table of contents technical data MC68HC08JB1 ? rev. 1.0 8 table of contents motorola section 4. read-only memory (rom) 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 section 5. configuration register (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 section 6. central processor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.7 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
table of contents MC68HC08JB1 ? rev. 1.0 technical data motorola table of contents 9 section 7. oscillator (osc) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3 oscillator external connections . . . . . . . . . . . . . . . . . . . . . . . . 72 7.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 73 7.4.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . 73 7.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 73 7.4.4 external clock source (oscxclk) . . . . . . . . . . . . . . . . . . . 73 7.4.5 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 section 8. system integration module (sim) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 78 8.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.3.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . . 78 8.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . 79 8.4 reset and system initialization. . . . . . . . . . . . . . . . . . . . . . . . . 79 8.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.4.2 active resets from internal sources . . . . . . . . . . . . . . . . . . 80 8.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.4.2.2 computer operating properly (cop) reset . . . . . . . . . . 82 8.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . 83 8.4.2.6 universal serial bus reset . . . . . . . . . . . . . . . . . . . . . . . 83 8.4.2.7 registers values after different resets . . . . . . . . . . . . . 84 8.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.5.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . 85
table of contents technical data MC68HC08JB1 ? rev. 1.0 10 table of contents motorola 8.5.2 sim counter during stop mode recovery . . . . . . . . . . . . . . 85 8.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . . 85 8.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.6.2 interrupt status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.6.2.1 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . 90 8.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.8.1 reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 section 9. universal serial bus module (usb) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.5.1 usb protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.5.1.1 sync pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.5.1.2 packet identifier field . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.5.1.3 address field (addr) . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.5.1.4 endpoint field (endp). . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.5.1.5 cyclic redundancy check (crc) . . . . . . . . . . . . . . . . . 102 9.5.1.6 end-of-packet (eop) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.5.2 reset signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.5.3 suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.5.4 resume after suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.5.4.1 host initiated resume . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.5.4.2 usb reset signalling. . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.5.4.3 remote wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
table of contents MC68HC08JB1 ? rev. 1.0 technical data motorola table of contents 11 9.5.5 low-speed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.6 clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.7 hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.7.1 voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.7.2 usb transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.7.2.1 output driver characteristics . . . . . . . . . . . . . . . . . . . . . 108 9.7.2.2 low speed (1.5 mbps) driver characteristics . . . . . . . . 108 9.7.2.3 receiver data jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.7.2.4 data source jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.7.2.5 data signal rise and fall time . . . . . . . . . . . . . . . . . . . 110 9.7.3 usb control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.8 i/o register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.8.1 usb address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.8.2 usb interrupt register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.8.3 usb interrupt register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.8.4 usb interrupt register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.8.5 usb control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.8.6 usb control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.8.7 usb control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.8.8 usb control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.8.9 usb control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.8.10 usb status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.8.11 usb status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.8.12 usb endpoint 0 data registers . . . . . . . . . . . . . . . . . . . . . 130 9.8.13 usb endpoint 1 data registers . . . . . . . . . . . . . . . . . . . . . 131 9.8.14 usb endpoint 2 data registers . . . . . . . . . . . . . . . . . . . . . 132 9.9 usb interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.9.1 usb end-of-transaction interrupt . . . . . . . . . . . . . . . . . . . 133 9.9.1.1 receive control endpoint 0 . . . . . . . . . . . . . . . . . . . . . . 134 9.9.1.2 transmit control endpoint 0 . . . . . . . . . . . . . . . . . . . . . 136 9.9.1.3 transmit endpoint 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.9.1.4 transmit endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.9.2 resume interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.9.3 end-of-packet interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
table of contents technical data MC68HC08JB1 ? rev. 1.0 12 table of contents motorola section 10. timer interface module (tim) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 144 10.5.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . 144 10.5.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . 145 10.5.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . 146 10.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 147 10.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.8.1 tim clock pin (pte0/tclk) . . . . . . . . . . . . . . . . . . . . . . . 151 10.8.2 tim channel i/o pins (pte1/tch0:pte2/tch1) . . . . . . . 151 10.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.9.1 tim status and control register . . . . . . . . . . . . . . . . . . . . 152 10.9.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 10.9.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . 155 10.9.4 tim channel status and control registers . . . . . . . . . . . . 156 10.9.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 section 11. input/output ports (i/o) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 11.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
table of contents MC68HC08JB1 ? rev. 1.0 technical data motorola table of contents 13 11.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 164 11.4 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11.4.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11.4.2 data direction register c. . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.5 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.5.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.5.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.6 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.6.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.6.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.7 port options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.7.1 port option control register . . . . . . . . . . . . . . . . . . . . . . . 175 section 12. external interrupt (irq) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 12.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 12.6 pte4/d?pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 12.7 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 181 12.8 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 182 12.9 irq option control register. . . . . . . . . . . . . . . . . . . . . . . . . . 183 section 13. keyboard interrupt module (kbi) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 13.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
table of contents technical data MC68HC08JB1 ? rev. 1.0 14 table of contents motorola 13.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 13.6 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.8 keyboard module during break interrupts . . . . . . . . . . . . . . . 191 13.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.9.1 keyboard status and control register. . . . . . . . . . . . . . . . 191 13.9.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 193 section 14. computer operating properly (cop) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.1 oscxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.4.8 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . 198 14.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
table of contents MC68HC08JB1 ? rev. 1.0 technical data motorola table of contents 15 section 15. low voltage inhibit (lvi) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 15.4 lvi control register (config) . . . . . . . . . . . . . . . . . . . . . . . 202 15.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 15.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 15.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 section 16. electrical specifications 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 16.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 204 16.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.6 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 206 16.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.8 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.9 usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 208 16.10 usb low-speed source electrical characteristics . . . . . . . . 209 16.11 usb signaling levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.12 timer interface module characteristics . . . . . . . . . . . . . . . . . 210 section 17. mechanical specifications 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 17.3 20-pin dual in-line package (pdip) . . . . . . . . . . . . . . . . . . . 212 17.4 20-pin small outline integrated circuit (soic) . . . . . . . . . . . 212
table of contents technical data MC68HC08JB1 ? rev. 1.0 16 table of contents motorola
MC68HC08JB1 ? rev. 1.0 technical data motorola list of figures 17 technical data ?MC68HC08JB1 list of figures figure title page 1-1 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1-2 20-pin pdip/soic assignments . . . . . . . . . . . . . . . . . . . . . . . . 27 1-3 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1-4 regulator supply capacitor configuration . . . . . . . . . . . . . . . . 28 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2-2 control, status, and data registers . . . . . . . . . . . . . . . . . . . . . 36 5-1 configuration register (config). . . . . . . . . . . . . . . . . . . . . . . 50 6-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 58 7-1 oscillator external connections . . . . . . . . . . . . . . . . . . . . . . . . 72 8-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8-2 sim i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8-3 sim clock signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8-6 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8-8 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8-9 interrupt entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8-10 interrupt recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . . 88
list of figures technical data MC68HC08JB1 ? rev. 1.0 18 list of figures motorola figure title page 8-12 interrupt status register 1 (int1). . . . . . . . . . . . . . . . . . . . . . . 90 8-13 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8-14 wait recovery from interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8-15 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . . 92 8-16 stop mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8-17 stop mode recovery from interrupt . . . . . . . . . . . . . . . . . . . . . 93 8-18 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9-1 usb block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9-2 supported transaction types per endpoint. . . . . . . . . . . . . . . 99 9-3 supported usb packet types . . . . . . . . . . . . . . . . . . . . . . . . 100 9-4 sync pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9-5 sop, sync signaling, and voltage levels . . . . . . . . . . . . . . . 101 9-6 eop transaction voltage levels . . . . . . . . . . . . . . . . . . . . . . 103 9-7 eop width timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9-8 external low-speed device configuration . . . . . . . . . . . . . . . 106 9-9 regulator electrical connections . . . . . . . . . . . . . . . . . . . . . . 107 9-10 receiver characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9-11 differential input sensitivity range. . . . . . . . . . . . . . . . . . . . . 109 9-12 data jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9-13 data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . 110 9-14 usb i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9-15 usb address register (uaddr) . . . . . . . . . . . . . . . . . . . . . . 115 9-16 usb interrupt register 0 (uir0) . . . . . . . . . . . . . . . . . . . . . . . 116 9-17 usb interrupt register 1 (uir1) . . . . . . . . . . . . . . . . . . . . . . . 117 9-18 usb interrupt register 2 (uir2) . . . . . . . . . . . . . . . . . . . . . . . 120 9-19 usb control register 0 (ucr0) . . . . . . . . . . . . . . . . . . . . . . . 121 9-20 usb control register 1 (ucr1) . . . . . . . . . . . . . . . . . . . . . . . 122 9-21 usb control register 2 (ucr2) . . . . . . . . . . . . . . . . . . . . . . . 123 9-22 usb control register 3 (ucr3) . . . . . . . . . . . . . . . . . . . . . . . 125 9-23 usb control register 4 (ucr4) . . . . . . . . . . . . . . . . . . . . . . . 127 9-24 usb status register 0 (usr0). . . . . . . . . . . . . . . . . . . . . . . . 128 9-25 usb status register 2 (usr1). . . . . . . . . . . . . . . . . . . . . . . . 129 9-26 usb endpoint 0 data register (ue0d0?e0d7). . . . . . . . . . 130 9-27 usb endpoint 1 data register (ue1d0?e1d7). . . . . . . . . . 131 9-28 usb endpoint 2 data register (ue2d0?e2d7). . . . . . . . . . 132
list of figures MC68HC08JB1 ? rev. 1.0 technical data motorola list of figures 19 figure title page 9-29 out token data flow for receive endpoint 0. . . . . . . . . . . . 134 9-30 setup token data flow for receive endpoint 0 . . . . . . . . . 135 9-31 in token data flow for transmit endpoint 0 . . . . . . . . . . . . . 136 9-32 in token data flow for transmit endpoint 1 . . . . . . . . . . . . . 137 10-1 tim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10-2 tim i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10-3 pwm period and pulse width . . . . . . . . . . . . . . . . . . . . . . . . 146 10-4 tim status and control register (tsc) . . . . . . . . . . . . . . . . . 152 10-5 tim counter registers (tcnth:tcntl) . . . . . . . . . . . . . . . . 154 10-6 tim counter modulo registers (tmodh:tmodl). . . . . . . . . 155 10-7 tim channel status and control registers (tsc0:tsc1) . . . 156 10-8 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10-9 tim channel registers (tch0h/l:tch1h/l). . . . . . . . . . . . . 160 11-1 i/o port register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 162 11-2 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . . . 163 11-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 164 11-4 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 11-5 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11-6 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . . . . 167 11-7 port c i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11-8 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11-9 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . 169 11-10 port d i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11-11 port e data register (pte) . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11-12 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . . . 173 11-13 port e i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11-14 port option control register (pocr). . . . . . . . . . . . . . . . . . . 175 12-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 179 12-2 irq i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 179 12-3 irq status and control register (iscr) . . . . . . . . . . . . . . . . 182 12-4 irq option control register (iocr) . . . . . . . . . . . . . . . . . . . 183 13-1 keyboard module block diagram . . . . . . . . . . . . . . . . . . . . . . 187
list of figures technical data MC68HC08JB1 ? rev. 1.0 20 list of figures motorola figure title page 13-2 keyboard status and control register (kbscr) . . . . . . . . . . 192 13-3 keyboard interrupt enable register (kbier) . . . . . . . . . . . . . 193 14-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14-2 configuration register (config). . . . . . . . . . . . . . . . . . . . . . 198 14-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . 199 15-1 lvi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 15-2 configuration register (config). . . . . . . . . . . . . . . . . . . . . . 202 17-1 20-pin pdip (case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 17-2 20-pin soic (case #751d) . . . . . . . . . . . . . . . . . . . . . . . . . . 212
MC68HC08JB1 ? rev. 1.0 technical data motorola list of tables 21 technical data ?MC68HC08JB1 list of tables table title page 1-1 summary of pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8-1 sim module signal name conventions . . . . . . . . . . . . . . . . . . 77 8-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8-3 registers not affected by normal reset. . . . . . . . . . . . . . . . . . 84 8-4 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9-1 usb module pin name conventions . . . . . . . . . . . . . . . . . . . . 98 9-2 supported packet identifiers. . . . . . . . . . . . . . . . . . . . . . . . . . 101 10-1 tim pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 10-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 158 11-1 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 11-2 port c pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11-3 port d pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11-4 port e pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13-1 kbi pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . 186 13-2 i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
list of tables technical data MC68HC08JB1 ? rev. 1.0 22 list of tables motorola
MC68HC08JB1 ? rev. 1.0 technical data motorola general description 23 technical data ?MC68HC08JB1 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.1 power supply pins (v dd , v ss ) . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.2 voltage regulator out (v reg ) . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.3 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 29 1.5.4 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.5 external interrupt pins (irq , pte4/d? . . . . . . . . . . . . . . . . 29 1.5.6 port a input/output (i/o) pins (pta7/kba7?ta0/kba0). . 29 1.5.7 port c i/o pins (ptc0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.8 port d i/o pins (ptd0/1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.9 port e i/o pins (pte4/d? pte3/d+, pte1/tch0) . . . . . . . 30 1.2 introduction the MC68HC08JB1 is a member of the low-cost, high-performance m68hc08 family of 8-bit microcontroller units (mcus). the m68hc08 family is based on the customer-specified integrated circuit (csic) design strategy. all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types.
general description technical data MC68HC08JB1 ? rev. 1.0 24 general description motorola 1.3 features features of the MC68HC08JB1 include: high-performance m68hc08 architecture fully upward-compatible object code with m6805, m146805, and m68hc05 families 3-mhz internal bus frequency 5,632 bytes of on-chip read-only memory (rom) 128 bytes of on-chip random-access memory (ram) rom data security 1 13 general-purpose 3.3v input/output (i/o) pins, including: 8 keyboard interrupts on port a 50ma direct drive for infrared led on ptd0/1 pin 10ma high current drive for ps/2 connection on 2 pins (with usb module disabled) 16-bit, 2-channel timer interface module (tim) with selectable input capture, output compare, pwm capability on one channel full universal serial bus specification 1.1 low-speed functions: 1.5 mbps data rate on-chip 3.3v regulator endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer endpoint 1 with 8-byte transmit buffer endpoint 2 with 8-byte transmit buffer system protection features: optional computer operating properly (cop) reset optional low-voltage detection with reset illegal opcode detection with reset illegal address detection with reset 1. no security feature is absolutely secure. however, motorola? strategy is to make reading or copying the rom difficult for unauthorized users.
general description mcu block diagram MC68HC08JB1 ? rev. 1.0 technical data motorola general description 25 low-power design (fully static with stop and wait modes) master reset pin with internal pull-up and power-on reset external asynchronous interrupt pin with internal pull-up (irq ) 20-pin plastic dual-in-line package (dip), or 20-pin small outline integrated circuit package (soic) features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications efficient c language support 1.4 mcu block diagram figure 1-1 shows the structure of the MC68HC08JB1.
general description technical data MC68HC08JB1 ? rev. 1.0 26 general description motorola figure 1-1. mcu block diagram system integration module timer interface module low voltage inhibit module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ?64 bytes user rom ?5,632 bytes user ram ?128 bytes monitor rom ?464 bytes user vectors ?32 bytes irq module power pta ddra internal bus osc1 osc2 (1), (2) rst (1), (3) irq v dd v ss pta7/kba7 pta0/kba0 (3) pte4/d? (3) pte3/d+ (3) pte1/tch0 (3) ptd ddrd ptd0/1 usb module usb endpoint 0, 1, 2 internal voltage regulator v reg 3.3 v (1) pins have 5v logic. (2) pins have integrated pullup device. (3) pins have software configurable pull-up device. ls usb transceiver oscillator ptc ddrc ptc0 (3) keyboard interrupt module power-on reset module pte ddre
general description pin assignments MC68HC08JB1 ? rev. 1.0 technical data motorola general description 27 1.5 pin assignments figure 1-2. 20-pin pdip/soic assignments note: the ptd0 and ptd1 internal pads are bonded together to ptd0/1 pin. 1.5.1 power supply pins (v dd , v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu as figure 1-3 shows. place the bypass capacitors as close to the mcu power pins as possible. use high-frequency-response ceramic capacitors for c bypass . c bulk are optional bulk current bypass capacitors for use in applications that require the port pins to source high current levels. 1 2 3 4 5 6 7 20 19 18 17 16 15 14 13 12 11 8 9 10 osc1 pta0/kba0 rst pta1/kba1 pta2/kba2 pta3/kba3 pta4/kba4 pta5/kba5 pta6/kba6 pta7/kba7 irq osc2 v reg v dd ptd0/1 pte1/tch0 pte3/d+ pte4/d ptc0 v ss
general description technical data MC68HC08JB1 ? rev. 1.0 28 general description motorola figure 1-3. power supply bypassing 1.5.2 voltage regulator out (v reg ) v reg is the 3.3 v output of the on-chip voltage regulator. v reg is used internally for the mcu operation and the usb data driver. it is also used to supply the voltage for the external pullup resistor required on the usb? d?line. the v reg pin requires an external bulk capacitor 4.7 m f or larger and a 0.1 m f ceramic bypass capacitor as figure 1-4 shows. place the bypass capacitors as close to the v reg pin as possible. figure 1-4. regulator supply capacitor configuration mcu c bulk c bypass 0.1 m f + note: values shown are typical values. v dd v dd v ss mcu v reg c regbulk c regbypass 0.1 m f v ss + v reg > 4.7 m f
general description pin assignments MC68HC08JB1 ? rev. 1.0 technical data motorola general description 29 1.5.3 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the connections for the on-chip oscillator circuit. 1.5.4 external reset pin (rst ) a logic zero on the rst pin forces the mcu to a known start-up state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. the rst pin contains an internal pullup device to v dd . (see section 8. system integration module (sim) .) 1.5.5 external interrupt pins (irq , pte4/d? irq is an asynchronous external interrupt pin. irq is also the pin to enter monitor mode. the irq pin contains a software configurable pullup device to v dd . pte4/d?can be programmed to trigger the irq1 interrupt. (see section 12. external interrupt (irq) .) 1.5.6 port a input/output (i/o) pins (pta7/kba7?ta0/kba0) pta7/kba7 ?ta0/kba0 are general-purpose bidirectional i/o port pins. (see section 11. input/output ports (i/o) .) each pin contains a software configurable pullup device to v reg when the pin is configured as an input. (see 11.7 port options .) any or all of the port a pins can be programmed to serve as external interrupt pins. (see section 13. keyboard interrupt module (kbi) .) 1.5.7 port c i/o pins (ptc0) ptc0 is a general-purpose bidirectional i/o port pin. (see section 11. input/output ports (i/o) .) the pin contains a software configurable pullup device to v reg when the pin is configured as an input. (see 11.7 port options .)
general description technical data MC68HC08JB1 ? rev. 1.0 30 general description motorola 1.5.8 port d i/o pins (ptd0/1) ptd0/1 is a general-purpose bidirectional open drain i/o port pin. (see section 11. input/output ports (i/o) .) this pin is software configurable to be 50ma infrared led drive port pin. (see 11.7 port options .) 1.5.9 port e i/o pins (pte4/d? pte3/d+, pte1/tch0) port e is a 3-bit special function port that shares two of its pins with the usb data bus d+ and d? and one of its pins with the timer interface module. all port e pins contain software configurable pullup devices. when the usb module is disabled, the pte4/d?and pte3/d+ pins become 10ma high current open drain drive pins and contain 5k w software configurable pullup devices to v dd . the pte4 pin can be enabled to trigger the irq1 interrupt. when the usb module is enabled, the pte4/d?and pte3/d+ pins become the usb d?and d+ pins. the usb d?pin contains a 1.5k w software configurable pullup device to v reg . (see section 10. timer interface module (tim) , section 9. universal serial bus module (usb) and section 11. input/output ports (i/o) .) summary of the pin functions are provided in table 1-1 .
general description pin assignments MC68HC08JB1 ? rev. 1.0 technical data motorola general description 31 table 1-1. summary of pin functions pin name pin description in/out voltage level v dd power supply. in 4.0 to 5.5v v ss power supply ground. out 0v v reg 3.3v regulated output from mcu. out v reg (3.3v) rst reset input, active low. with internal pull-up (to v dd ) and schmitt trigger input. in/out v dd irq external irq pin; with software programmable internal pull-up (to v dd ) and schmitt trigger input. in v dd used for mode entry selection. in v reg to v dd +v hi osc1 crystal oscillator input. in v reg osc2 crystal oscillator output; inverting of osc1 signal. out v reg pta[0:7] 8-bit general purpose i/o port. in/out v reg shared with 8 keyboard interrupts kba[0:7]. in v reg each pin has programmable internal pull-up to v reg . in v reg pta7 pin input tolerance. in v dd ptc0 general purpose i/o pin. in/out v reg pin has programmable internal pull-up device to v reg . in v reg ptd0/1 general purpose i/o pin. in/out open-drain con?urable to 50 ma sink for infrared led. out v reg or v dd pte1/tch0 pte3/d+ pte4/d 3-bit general purpose i/o port. in/out v reg pte1 has programmable internal pull-up to v reg . in/out v reg pte[3:4] has programmable internal pull-up to v reg . in v reg pte4 enabled for irq1 interrupt in v dd
general description technical data MC68HC08JB1 ? rev. 1.0 32 general description motorola
MC68HC08JB1 ? rev. 1.0 technical data motorola memory map 33 technical data ?MC68HC08JB1 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 5,632 bytes of user rom 128 bytes of ram 32 bytes of user-defined vectors 464 bytes of monitor rom
memory map technical data MC68HC08JB1 ? rev. 1.0 34 memory map motorola $0000 $003f i/o registers 64 bytes $0040 $007f unimplemented 64 bytes $0080 $00ff ram 128 bytes $0100 $e5ff unimplemented 58,624 bytes $e600 $fbff user rom 5,632 bytes $fc00 $fdff reserved 512 bytes $fe00 reserved $fe01 reset status register (rsr) $fe02 reserved $fe03 reserved $fe04 interrupt status register 1 (int1) $fe05 reserved $fe06 $fe0f reserved $fe10 $ffdf monitor rom 464 bytes $ffe0 $ffff user rom vectors 32 bytes figure 2-1. memory map
memory map i/o section MC68HC08JB1 ? rev. 1.0 technical data motorola memory map 35 2.3 i/o section addresses $0000?003f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have these addresses: $fe00 (reserved) $fe01 (reset status register, rsr) $fe02 (reserved) $fe03 (reserved) $fe04 (interrupt status register 1, int1) $fe05 (reserved) $fe06 to fe0f (reserved) $ffff (cop control register, copctl) 2.4 monitor rom the 464 bytes at addresses $fe10?ffdf are reserved rom addresses that contain the instructions for the monitor functions.
memory map technical data MC68HC08JB1 ? rev. 1.0 36 memory map motorola addr. register name bit 7 654321 bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 unimplemented read: write: reset: $0002 port c data register (ptc) read: 0000000 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: 000000 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0* 0000000 * ddra7 bit is reset by por or lvi reset only. $0005 unimplemented read: write: reset: $0006 data direction register c (ddrc) read: 0000000 ddrc0 write: reset: 00000000 $0007 data direction register d (ddrd) read: 000000 ddrd1 ddrd0 write: reset: 00000000 $0008 port e data register (pte) read: 0 0 0 pte4 pte3 0 pte1 0 write: reset: unaffected by reset $0009 data direction register e (ddre) read: 0 0 0 ddre4 ddre3 0 ddre1 0 write: reset: 00000000 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, and data registers (sheet 1 of 8)
memory map monitor rom MC68HC08JB1 ? rev. 1.0 technical data motorola memory map 37 $000a tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 $000b unimplemented read: write: $000c tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: 00000000 $000d tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: 00000000 $000e tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: 11111111 $000f tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: 11111111 $0010 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 $0011 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0012 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0013 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 addr. register name bit 7 654321 bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, and data registers (sheet 2 of 8)
memory map technical data MC68HC08JB1 ? rev. 1.0 38 memory map motorola $0014 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0015 tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0016 keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset: 00000000 $0017 keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset: 00000000 $0018 usb interrupt register 2 (uir2) read: 00000000 write: eopfr rstfr txd2fr tdx1fr resumfr txd0fr rxd0fr reset: 00000000 $0019 usb control register 2 (ucr2) read: t2seq stall2 tx2e 0 tp2siz3 tp2siz2 tp2siz1 tp2siz0 write: reset: 00000000 $001a usb control register 3 (ucr3) read: tx1st 0 ostall0 istall0 0 pullen enable2 enable1 write: tx1str reset: 000000*00 * pullen bit is reset by por or lvi reset only. $001b usb control register 4 (ucr4) read: 00000 fusbo fdp fdm write: reset: 00000000 $001c irq option control register (iocr) read: 00000 pte4if pte4ie irqpd write: reset: 00000000 $001d port option control register (pocr) read: pte20p 0 ptdildd pte4p pte3p pcp 0 pa p write: reset: 00000000 addr. register name bit 7 654321 bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, and data registers (sheet 3 of 8)
memory map monitor rom MC68HC08JB1 ? rev. 1.0 technical data motorola memory map 39 $001e irq status and control register (iscr) read: 0000 irqf1 0 imask1 mode1 write: ack1 reset: 00000000 $001f configuration register (config) ? read: 0 0 urstd lvid ssrec coprs stop copd write: reset: 00000000 ? one-time writable register after each reset. urstd and lvid bits are reset by por or lvi reset only. $0020 usb endpoint 0 data register 0 (ue0d0) read: ue0r07 ue0r06 ue0r05 ue0r04 ue0r03 ue0r02 ue0r01 ue0r00 write: ue0t07 ue0t06 ue0t05 ue0t04 ue0t03 ue0t02 ue0t01 ue0t00 reset: unaffected by reset $0021 usb endpoint 0 data register 1 (ue0d1) read: ue0r17 ue0r16 ue0r15 ue0r14 ue0r13 ue0r12 ue0r11 ue0r10 write: ue0t17 ue0t16 ue0t15 ue0t14 ue0t13 ue0t12 ue0t11 ue0t10 reset: unaffected by reset $0022 usb endpoint 0 data register 2 (ue0d2) read: ue0r27 ue0r26 ue0r25 ue0r24 ue0r23 ue0r22 ue0r21 ue0r20 write: ue0t27 ue0t26 ue0t25 ue0t24 ue0t23 ue0t22 ue0t21 ue0t20 reset: unaffected by reset $0023 usb endpoint 0 data register 3 (ue0d3) read: ue0r37 ue0r36 ue0r35 ue0r34 ue0r33 ue0r32 ue0r31 ue0r30 write: ue0t37 ue0t36 ue0t35 ue0t34 ue0t33 ue0t32 ue0t31 ue0t30 reset: unaffected by reset $0024 usb endpoint 0 data register 4 (ue0d4) read: ue0r47 ue0r46 ue0r45 ue0r44 ue0r43 ue0r42 ue0r41 ue0r40 write: ue0t47 ue0t46 ue0t45 ue0t44 ue0t43 ue0t42 ue0t41 ue0t40 reset: unaffected by reset $0025 usb endpoint 0 data register 5 (ue0d5) read: ue0r57 ue0r56 ue0r55 ue0r54 ue0r53 ue0r52 ue0r51 ue0r50 write: ue0t57 ue0t56 ue0t55 ue0t54 ue0t53 ue0t52 ue0t51 ue0t50 reset: unaffected by reset $0026 usb endpoint 0 data register 6 (ue0d6) read: ue0r67 ue0r66 ue0r65 ue0r64 ue0r63 ue0r62 ue0r61 ue0r60 write: ue0t67 ue0t66 ue0t65 ue0t64 ue0t63 ue0t62 ue0t61 ue0t60 reset: unaffected by reset $0027 usb endpoint 0 data register 7 (ue0d7) read: ue0r77 ue0r76 ue0r75 ue0r74 ue0r73 ue0r72 ue0r71 ue0r70 write: ue0t77 ue0t76 ue0t75 ue0t74 ue0t73 ue0t72 ue0t71 ue0t70 reset: unaffected by reset addr. register name bit 7 654321 bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, and data registers (sheet 4 of 8)
memory map technical data MC68HC08JB1 ? rev. 1.0 40 memory map motorola $0028 usb endpoint 1 data register 0 (ue1d0) read: write: ue1t07 ue1t06 ue1t05 ue1t04 ue1t03 ue1t02 ue1t01 ue1t00 reset: unaffected by reset $0029 usb endpoint 1 data register 1 (ue1d1) read: write: ue1t17 ue1t16 ue1t15 ue1t14 ue1t13 ue1t12 ue1t11 ue1t10 reset: unaffected by reset $002a usb endpoint 1 data register 2 (ue1d2) read: write: ue1t27 ue1t26 ue1t25 ue1t24 ue1t23 ue1t22 ue1t21 ue1t20 reset: unaffected by reset $002b usb endpoint 1 data register 3 (ue1d3) read: write: ue1t37 ue1t36 ue1t35 ue1t34 ue1t33 ue1t32 ue1t31 ue1t30 reset: unaffected by reset $002c usb endpoint 1 data register 4 (ue1d4) read: write: ue1t47 ue1t46 ue1t45 ue1t44 ue1t43 ue1t42 ue1t41 ue1t40 reset: unaffected by reset $002d usb endpoint 1 data register 5 (ue1d5) read: write: ue1t57 ue1t56 ue1t55 ue1t54 ue1t53 ue1t52 ue1t51 ue1t50 reset: unaffected by reset $002e usb endpoint 1 data register 6 (ue1d6) read: write: ue1t67 ue1t66 ue1t65 ue1t64 ue1t63 ue1t62 ue1t61 ue1t60 reset: unaffected by reset $002f usb endpoint 1 data register 7 (ue1d7) read: write: ue1t77 ue1t76 ue1t75 ue1t74 ue1t73 ue1t72 ue1t71 ue1t70 reset: unaffected by reset $0030 usb endpoint 2 data register 0 (ue2d0) read: write: ue2t07 ue2t06 ue2t05 ue2t04 ue2t03 ue2t02 ue2t01 ue2t00 reset: unaffected by reset $0031 usb endpoint 2 data register 1 (ue2d1) read: write: ue2t17 ue2t16 ue2t15 ue2t14 ue2t13 ue2t12 ue2t11 ue2t10 reset: unaffected by reset addr. register name bit 7 654321 bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, and data registers (sheet 5 of 8)
memory map monitor rom MC68HC08JB1 ? rev. 1.0 technical data motorola memory map 41 $0032 usb endpoint 2 data register 2 (ue2d2) read: write: ue2t27 ue2t26 ue2t25 ue2t24 ue2t23 ue2t22 ue2t21 ue2t20 reset: unaffected by reset $0033 usb endpoint 2 data register 3 (ue2d3) read: write: ue2t37 ue2t36 ue2t35 ue2t34 ue2t33 ue2t32 ue2t31 ue2t30 reset: unaffected by reset $0034 usb endpoint 2 data register 4 (ue2d4) read: write: ue2t47 ue2t46 ue2t45 ue2t44 ue2t43 ue2t42 ue2t41 ue2t40 reset: unaffected by reset $0035 usb endpoint 2 data register 5 (ue2d5) read: write: ue2t57 ue2t56 ue2t55 ue2t54 ue2t53 ue2t52 ue2t51 ue2t50 reset: unaffected by reset $0036 usb endpoint 2 data register 6 (ue2d6) read: write: ue2t67 ue2t66 ue2t65 ue2t64 ue2t63 ue2t62 ue2t61 ue2t60 reset: unaffected by reset $0037 usb endpoint 2 data register 7 (ue2d7) read: write: ue2t77 ue2t76 ue2t75 ue2t74 ue2t73 ue2t72 ue2t71 ue2t70 reset: unaffected by reset $0038 usb address register (uaddr) read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset: 0* 0000000 * usben bit is reset by por or lvi reset only. $0039 usb interrupt register 0 (uir0) read: eopie suspnd txd2ie 0 txd1ie 0 txd0ie rxd0ie write: reset: 00000000 $003a usb interrupt register 1 (uir1) read: eopf rstf txd2f 0 txd1f resumf txd0f rxd0f write: reset: 00000000 $003b usb control register 0 (ucr0) read: t0seq 0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset: 00000000 addr. register name bit 7 654321 bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, and data registers (sheet 6 of 8)
memory map technical data MC68HC08JB1 ? rev. 1.0 42 memory map motorola $003c usb control register 1 (ucr1) read: t1seq stall1 tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset: 00000000 $003d usb status register 0 (usr0) read: r0seq setup 0 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: reset: unaffected by reset $003e usb status register 1 (usr1) read: 0 txack txnak txstl 0000 write: reset: 00000000 $003f unimplemented read: write: $fe00 reserved read: rrrrrrrr write: $fe01 reset status register (rsr) read: por pin cop ilop ilad usb lvi 0 write: por: 10000000 $fe02 reserved read: rrrrrrrr write: $fe03 reserved read: rrrrrrrr write: $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write: rrrrrrrr reset: 00000000 $fe05 reserved read: rrrrrrrr write: addr. register name bit 7 654321 bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, and data registers (sheet 7 of 8)
memory map monitor rom MC68HC08JB1 ? rev. 1.0 technical data motorola memory map 43 table 2-1 is a list of vector locations. $fe06 $fe0f reserved read: rrrrrrrr write: $ffff cop control register (copctl) read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset addr. register name bit 7 654321 bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, and data registers (sheet 8 of 8) table 2-1. vector addresses vector priority vector address vector lowest if6 $fff0 keyboard vector (high) $fff1 keyboard vector (low) if5 $fff2 tim over?w vector (high) $fff3 tim over?w vector (low) if4 $fff4 tim channel 1 vector (high) $fff5 tim channel 1 vector (low) if3 $fff6 tim channel 0 vector (high) $fff7 tim channel 0 vector (low) if1 $fff8 irq1 vector (high) $fff9 irq1 vector (low) if2 $fffa usb vector (high) $fffb usb vector (low) $fffc swi vector (high) $fffd swi vector (low) $fffe reset vector (high) highest $ffff reset vector (low)
memory map technical data MC68HC08JB1 ? rev. 1.0 44 memory map motorola
MC68HC08JB1 ? rev. 1.0 technical data motorola random-access memory (ram) 45 technical data ?MC68HC08JB1 section 3. random-access memory (ram) 3.1 contents 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2 introduction this section describes the 128 bytes of ram. 3.3 functional description addresses $0080?00ff are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note: for correct operation, the stack pointer must point only to ram locations. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 family compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation.
random-access memory (ram) technical data MC68HC08JB1 ? rev. 1.0 46 random-access memory (ram) motorola
MC68HC08JB1 ? rev. 1.0 technical data motorola read-only memory (rom) 47 technical data ?MC68HC08JB1 section 4. read-only memory (rom) 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2 introduction this section describes the 5,632 bytes of rom (read-only memory). 4.3 functional description these addresses are user rom locations: $e600 ?$fbff (5,632 bytes) $ffe0 ?$ffff (these locations are reserved for user-defined interrupt and reset vectors.) note: a security feature prevents viewing of the rom contents. 1 1. no security feature is absolutely secure. however, motorola? strategy is to make reading or copying the rom contents difficult for unauthorized users.
read-only memory (rom) technical data MC68HC08JB1 ? rev. 1.0 48 read-only memory (rom) motorola
MC68HC08JB1 ? rev. 1.0 technical data motorola configuration register (config) 49 technical data ?MC68HC08JB1 section 5. configuration register (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.2 introduction this section describes the configuration register (config). this write- once-after-reset register controls the following options: usb reset low voltage inhibit stop mode recovery time (2048 or 4096 oscxclk cycles) cop timeout period (2 18 ?2 4 or 2 13 ?2 4 oscxclk cycles) stop instruction computer operating properly module (cop)
con?uration register (config) technical data MC68HC08JB1 ? rev. 1.0 50 configuration register (config) motorola 5.3 functional description the configuration register is used in the initialization of various options. the configuration register can be written once after each reset. bit-5 and bit-4 are cleared by a por or lvi reset only. bit-3 to bit-0 are cleared during any reset. since the various options affect the operation of the mcu, it is recommended that this register be written immediately after reset. the configuration register is located at $001f. the configuration register may be read at any time. urstd ?usb reset disable bit urstd disables the usb reset signal generating an internal reset to the cpu and internal registers. instead, it will generate an interrupt request to the cpu. 1 = usb reset generates a usb interrupt request to cpu 0 = usb reset generates a chip reset lvid ?low voltage inhibit disable bit lvid disables the lvi circuit 1 = disable lvi circuit 0 = enable lvi circuit ssrec ?short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 2048 oscxclk cycles instead of a 4096 oscxclk cycle delay. 1 = stop mode recovery after 2048 oscxclk cycles 0 = stop mode recovery after 4096 oscxclk cycles address: $001f bit 7 654321 bit 0 read: 0 0 urstd lvid ssrec coprs stop copd write: reset: 0 0 0* 0* 0000 = unimplemented note: urstd and lvid bits are reset by por or lvi reset only. figure 5-1. configuration register (config)
configuration register (config) functional description MC68HC08JB1 ? rev. 1.0 technical data motorola configuration register (config) 51 note: exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal, do not set the ssrec bit. coprs ?cop rate select bit copd selects the cop timeout period. reset clears coprs. (see section 14. computer operating properly (cop) .) 1 = cop timeout period = (2 13 ?2 4 ) oscxclk cycles 0 = cop timeout period = (2 18 ?2 4 ) oscxclk cycles stop ?stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ?cop disable bit copd disables the cop module. (see section 14. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled
con?uration register (config) technical data MC68HC08JB1 ? rev. 1.0 52 configuration register (config) motorola
MC68HC08JB1 ? rev. 1.0 technical data motorola central processor unit (cpu) 53 technical data ?MC68HC08JB1 section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.7 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
central processor unit (cpu) technical data MC68HC08JB1 ? rev. 1.0 54 central processor unit (cpu) motorola 6.2 introduction the m68hc08 cpu (central processor unit) is an enhanced and fully object-code-compatible version of the m68hc05 cpu. the cpu08 reference manual (motorola document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 6.3 features feature of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 6-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes
central processor unit (cpu) cpu registers MC68HC08JB1 ? rev. 1.0 technical data motorola central processor unit (cpu) 55 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu registers are not part of the memory map. figure 6-1. cpu registers 6.4.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two? complement overflow flag v1 1h i nzc h x 0 0 0 0 7 15 15 15 70 bit 7 654321 bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a)
central processor unit (cpu) technical data MC68HC08JB1 ? rev. 1.0 56 central processor unit (cpu) motorola 6.4.2 index register the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, the cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. 6.4.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset: 00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x) bit 15 1413121110987654321 bit 0 read: write: reset: 0000000011111111 figure 6-4. stack pointer (sp)
central processor unit (cpu) cpu registers MC68HC08JB1 ? rev. 1.0 technical data motorola central processor unit (cpu) 57 note: the location of the stack is arbitrary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 6.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. program counter (pc)
central processor unit (cpu) technical data MC68HC08JB1 ? rev. 1.0 58 central processor unit (cpu) motorola 6.4.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to logic 1. the following paragraphs describe the functions of the condition code register. v ?overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ?half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add- with-carry (adc) operation. the half-carry flag is required for binary- coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 7 654321 bit 0 read: v1 1h i nzc write: reset: x 1 1x1xxx x = indeterminate figure 6-6. condition code register (ccr)
central processor unit (cpu) cpu registers MC68HC08JB1 ? rev. 1.0 technical data motorola central processor unit (cpu) 59 i ?interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ?negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ?zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result
central processor unit (cpu) technical data MC68HC08JB1 ? rev. 1.0 60 central processor unit (cpu) motorola c ?carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ?such as bit test and branch, shift, and rotate ?also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.5 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (motorola document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 6.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.6.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock
central processor unit (cpu) cpu during break interrupts MC68HC08JB1 ? rev. 1.0 technical data motorola central processor unit (cpu) 61 6.6.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the condition code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins running after the oscillator stabilization delay. 6.7 cpu during break interrupts if the break module is enabled, a break interrupt causes the cpu to execute the software interrupt instruction (swi) at the completion of the current cpu instruction. the program counter vectors to $fffc?fffd ($fefc?fefd in monitor mode). a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. 6.8 instruction set summary table 6-1 provides a summary of the m68hc08 instruction set. 6.9 opcode map the opcode map is provided in table 6-2 .
central processor unit (cpu) technical data MC68HC08JB1 ? rev. 1.0 62 central processor unit (cpu) motorola table 6-1. instruction set summary (sheet 1 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp ? (sp) + (16 ?m) imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x ? (h:x) + (16 ?m) imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a ? (a) & (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? (c) = 0 rel 24 rr 3 bclr n , opr clear bit n in m mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 c b0 b7 0 b0 b7 c
central processor unit (cpu) opcode map MC68HC08JB1 ? rev. 1.0 technical data motorola central processor unit (cpu) 63 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? (c) = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? (z) = 1 rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc ? (pc) + 2 + rel ? (n ? v) = 0 rel 90 rr 3 bgt opr branch if greater than (signed operands) pc ? (pc) + 2 + rel ? (z) | (n ? v) = 0 rel 92 rr 3 bhcc rel branch if half carry bit clear pc ? (pc) + 2 + rel ? (h) = 0 rel 28 rr 3 bhcs rel branch if half carry bit set pc ? (pc) + 2 + rel ? (h) = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? (c) | (z) = 0 rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc ? (pc) + 2 + rel ? (c) = 0 rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc ? (pc) + 2 + rel ? (z) | (n ? v ) = 1 rel 93 rr 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? (c) = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? (c) | (z) = 1 rel 23 rr 3 blt opr branch if less than (signed operands) pc ? (pc) + 2 + rel ? (n ? v ) = 1 rel 91 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? (i) = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? (n) = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? (i) = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? (z) = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? (n) = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel rel 20 rr 3 table 6-1. instruction set summary (sheet 2 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) technical data MC68HC08JB1 ? rev. 1.0 64 central processor unit (cpu) motorola brclr n , opr , rel branch if bit n in m clear pc ? (pc) + 3 + rel ? (mn) = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc ? (pc) + 3 + rel ? (mn) = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1 pc ? (pc) + rel rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc ? (pc) + 3 + rel ? (a) ?(m) = $00 pc ? (pc) + 3 + rel ? (a) ?(m) = $00 pc ? (pc) + 3 + rel ? (x) ?(m) = $00 pc ? (pc) + 3 + rel ? (a) ?(m) = $00 pc ? (pc) + 2 + rel ? (a) ?(m) = $00 pc ? (pc) + 4 + rel ? (a) ?(m) = $00 dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c ? 0 ?inh 98 1 cli clear interrupt mask i ? 0 0inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m ? $00 a ? $00 x ? $00 h ? $00 m ? $00 m ? $00 m ? $00 001 dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 6-1. instruction set summary (sheet 3 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) opcode map MC68HC08JB1 ? rev. 1.0 technical data motorola central processor unit (cpu) 65 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ?(m) imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (ones complement) m ? (m ) = $ff ?(m) a ? (a ) = $ff ?(m) x ? (x ) = $ff ?(m) m ? (m ) = $ff ?(m) m ? (m ) = $ff ?(m) m ? (m ) = $ff ?(m) 0 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ?(m:m + 1) imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ?(m) imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a ? (a) ?1 or m ? (m) ?1 or x ? (x) ?1 pc ? (pc) + 3 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 3 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 4 + rel ? (result) 1 0 dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m ? (m) ?1 a ? (a) ?1 x ? (x) ?1 m ? (m) ?1 m ? (m) ?1 m ? (m) ?1 dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a ? (h:a)/(x) h ? remainder inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a ? (a ? m) 0 imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction set summary (sheet 4 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) technical data MC68HC08JB1 ? rev. 1.0 66 central processor unit (cpu) motorola inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n ( n = 1, 2, or 3) push (pcl); sp ? (sp) ?1 push (pch); sp ? (sp) ?1 pc ? unconditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a ? (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ? ( m:m + 1 ) 0 imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x ? (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right 0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 table 6-1. instruction set summary (sheet 5 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0
central processor unit (cpu) opcode map MC68HC08JB1 ? rev. 1.0 technical data motorola central processor unit (cpu) 67 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination ? (m) source h:x ? (h:x) + 1 (ix+d, dix+) 0 dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a ? (x) (a) ??inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (twos complement) m ? ?m) = $00 ?(m) a ? ?a) = $00 ?(a) x ? ?x) = $00 ?(x) m ? ?m) = $00 ?(m) m ? ?m) = $00 ?(m) dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none inh 9d 1 nsa nibble swap a a ? (a[3:0]:a[7:4]) inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a ? (a) | (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp ? (sp) ?1 inh 87 2 pshh push h onto stack push (h); sp ? (sp) ?1 inh 8b 2 pshx push x onto stack push (x); sp ? (sp) ?1 inh 89 2 pula pull a from stack sp ? (sp + 1); pull ( a ) inh 86 2 pulh pull h from stack sp ? (sp + 1); pull ( h ) inh 8a 2 pulx pull x from stack sp ? (sp + 1); pull ( x ) inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp ? $ff inh 9c 1 table 6-1. instruction set summary (sheet 6 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c
central processor unit (cpu) technical data MC68HC08JB1 ? rev. 1.0 68 central processor unit (cpu) motorola rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp ? sp + 1 ; pull ( pch) sp ? sp + 1; pull (pcl) inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a ? (a) ?(m) ?(c) imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c ? 1 ?inh 99 1 sei set interrupt mask i ? 1 1inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m ? (a) 0 dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) ? (h:x) 0 dir 35 dd 4 stop enable irq pin; stop oscillator i ? 0; stop oscillator 0inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m ? (x) 0 dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a ? (a) ?(m) imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction set summary (sheet 7 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) opcode map MC68HC08JB1 ? rev. 1.0 technical data motorola central processor unit (cpu) 69 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1; push (x) sp ? (sp) ?1; push (a) sp ? (sp) ?1; push (ccr) sp ? (sp) ?1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1inh 83 9 tap transfer a to ccr ccr ? (a) inh 84 2 tax transfer a to x x ? (a) inh 97 1 tpa transfer ccr to a a ? (ccr) inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ?$00 or (x) ?$00 or (m) ?$00 0 dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x ? (sp) + 1 inh 95 2 txa transfer x to a a ? (x) inh 9f 1 txs transfer h:x to sp (sp) ? (h:x) ?1 inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressing mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u unde?ed h index register high byte v over?w bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ) negation (twos complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode sign extend ix1 indexed, 8-bit offset addressing mode ? loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit not affected table 6-1. instruction set summary (sheet 8 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) technical data MC68HC08JB1 ? rev. 1.0 70 central processor unit (cpu) motorola table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789 abcd9ede9eef 0 5 brset0 3 dir 4 bset0 2 dir 3 bra 2 rel 4 neg 2 dir 1 nega 1 inh 1 negx 1 inh 4 neg 2 ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1 inh 3 bge 2 rel 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 4 sub 3 ix2 5 sub 4 sp2 3 sub 2 ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3 dir 4 bclr0 2 dir 3 brn 2 rel 5 cbeq 3 dir 4 cbeqa 3 imm 4 cbeqx 3 imm 5 cbeq 3 ix1+ 6 cbeq 4 sp1 4 cbeq 2 ix+ 4 rts 1 inh 3 blt 2 rel 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 4 cmp 3 ix2 5 cmp 4 sp2 3 cmp 2 ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3 dir 4 bset1 2 dir 3 bhi 2 rel 5 mul 1 inh 7 div 1 inh 3 nsa 1 inh 2 daa 1 inh 3 bgt 2 rel 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 4 sbc 3 ix2 5 sbc 4 sp2 3 sbc 2 ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3 dir 4 bclr1 2 dir 3 bls 2 rel 4 com 2 dir 1 coma 1 inh 1 comx 1 inh 4 com 2 ix1 5 com 3 sp1 3 com 1ix 9 swi 1 inh 3 ble 2 rel 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 4 cpx 3 ix2 5 cpx 4 sp2 3 cpx 2 ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3 dir 4 bset2 2 dir 3 bcc 2 rel 4 lsr 2 dir 1 lsra 1 inh 1 lsrx 1 inh 4 lsr 2 ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1 inh 2 txs 1 inh 2 and 2 imm 3 and 2 dir 4 and 3 ext 4 and 3 ix2 5 and 4 sp2 3 and 2 ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3 dir 4 bclr2 2 dir 3 bcs 2 rel 4 sthx 2 dir 3 ldhx 3 imm 4 ldhx 2 dir 3 cphx 3 imm 4 cphx 2 dir 1 tpa 1 inh 2 tsx 1 inh 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 4 bit 3 ix2 5 bit 4 sp2 3 bit 2 ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3 dir 4 bset3 2 dir 3 bne 2 rel 4 ror 2 dir 1 rora 1 inh 1 rorx 1 inh 4 ror 2 ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1 inh 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 4 lda 3 ix2 5 lda 4 sp2 3 lda 2 ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3 dir 4 bclr3 2 dir 3 beq 2 rel 4 asr 2 dir 1 asra 1 inh 1 asrx 1 inh 4 asr 2 ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1 inh 1 ta x 1 inh 2 ais 2 imm 3 sta 2 dir 4 sta 3 ext 4 sta 3 ix2 5 sta 4 sp2 3 sta 2 ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3 dir 4 bset4 2 dir 3 bhcc 2 rel 4 lsl 2 dir 1 lsla 1 inh 1 lslx 1 inh 4 lsl 2 ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1 inh 1 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 4 eor 3 ix2 5 eor 4 sp2 3 eor 2 ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3 dir 4 bclr4 2 dir 3 bhcs 2 rel 4 rol 2 dir 1 rola 1 inh 1 rolx 1 inh 4 rol 2 ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1 inh 1 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 4 adc 3 ix2 5 adc 4 sp2 3 adc 2 ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3 dir 4 bset5 2 dir 3 bpl 2 rel 4 dec 2 dir 1 deca 1 inh 1 decx 1 inh 4 dec 2 ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1 inh 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 4 ora 3 ix2 5 ora 4 sp2 3 ora 2 ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3 dir 4 bclr5 2 dir 3 bmi 2 rel 5 dbnz 3 dir 3 dbnza 2 inh 3 dbnzx 2 inh 5 dbnz 3 ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1 inh 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 4 add 3 ix2 5 add 4 sp2 3 add 2 ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3 dir 4 bset6 2 dir 3 bmc 2 rel 4 inc 2 dir 1 inca 1 inh 1 incx 1 inh 4 inc 2 ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1 inh 1 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix d 5 brclr6 3 dir 4 bclr6 2 dir 3 bms 2 rel 3 tst 2 dir 1 tsta 1 inh 1 tstx 1 inh 3 tst 2 ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1 inh 4 bsr 2 rel 4 jsr 2 dir 5 jsr 3 ext 6 jsr 3 ix2 5 jsr 2 ix1 4 jsr 1ix e 5 brset7 3 dir 4 bset7 2 dir 3 bil 2 rel 5 mov 3dd 4 mov 2 dix+ 4 mov 3 imd 4 mov 2 ix+d 1 stop 1 inh * 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 4 ldx 3 ix2 5 ldx 4 sp2 3 ldx 2 ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3 dir 4 bclr7 2 dir 3 bih 2 rel 3 clr 2 dir 1 clra 1 inh 1 clrx 1 inh 3 clr 2 ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1 inh 1 txa 1 inh 2 aix 2 imm 3 stx 2 dir 4 stx 3 ext 4 stx 3 ix2 5 stx 4 sp2 3 stx 2 ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3 dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb
MC68HC08JB1 ? rev. 1.0 technical data motorola oscillator (osc) 71 technical data ?MC68HC08JB1 section 7. oscillator (osc) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3 oscillator external connections . . . . . . . . . . . . . . . . . . . . . . . . 72 7.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 73 7.4.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . 73 7.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 73 7.4.4 external clock source (oscxclk) . . . . . . . . . . . . . . . . . . . 73 7.4.5 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.2 introduction the oscillator circuit is designed for use with crystals or ceramic resonators. the oscillator circuit generates the crystal clock signal. the crystal oscillator output signal passes through the clock doubler. oscxclk is the output signal of the clock doubler. oscxclk is divided by two before being passed on to the system integration module (sim) for bus clock generation. figure 7-1 shows the structure of the oscillator. the oscillator requires various external components.
oscillator (osc) technical data MC68HC08JB1 ? rev. 1.0 72 oscillator (osc) motorola 7.3 oscillator external connections in its typical configuration, the oscillator requires five external components. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 7-1 . this figure shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) figure 7-1. oscillator external connections c1 c2 simoscen oscxclk x1 r s * * r s can be 0 (shorted) when used with higher-frequency crystals. refer to manufacturer? data. mcu from sim oscout to usb to sim clock doubler ? 2 to sim osc1 osc2 r b
oscillator (osc) i/o signals MC68HC08JB1 ? rev. 1.0 technical data motorola oscillator (osc) 73 the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be required for all ranges of operation, especially with high-frequency crystals. refer to the crystal manufacturer? data for more information. 7.4 i/o signals the following paragraphs describe the oscillator input/output (i/o) signals. 7.4.1 crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 7.4.2 crystal amplifier output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. 7.4.3 oscillator enable signal (simoscen) the simoscen signal comes from the system integration module (sim) and enables the oscillator. 7.4.4 external clock source (oscxclk) the crystal oscillator output signal passes through the clock doubler and oscxclk is the output signal of the clock doubler. oscxclk runs at twice the speed of the crystal (f xclk ). figure 7-1 shows only the logical relation of oscxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of oscxclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of oscxclk can be unstable at startup.
oscillator (osc) technical data MC68HC08JB1 ? rev. 1.0 74 oscillator (osc) motorola 7.4.5 oscillator out (oscout) the clock driven to the sim is oscxclk. this signal is driven to the sim for generation of the bus clocks used by the cpu and other modules on the mcu. oscout will be divided again in the sim and results in the internal bus frequency being one forth of the oscxclk frequency or one half of the crystal frequency. 7.5 low-power modes the wait and stop instructions put the mcu in low-power- consumption standby modes. 7.5.1 wait mode the wait instruction has no effect on the oscillator logic. oscxclk continues to drive to the sim module. 7.5.2 stop mode the stop instruction disables the oscxclk output.
MC68HC08JB1 ? rev. 1.0 technical data motorola system integration module (sim) 75 technical data ?MC68HC08JB1 section 8. system integration module (sim) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 78 8.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.3.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . . 78 8.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . 79 8.4 reset and system initialization. . . . . . . . . . . . . . . . . . . . . . . . . 79 8.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.4.2 active resets from internal sources . . . . . . . . . . . . . . . . . . 80 8.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.4.2.2 computer operating properly (cop) reset . . . . . . . . . . 82 8.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . 83 8.4.2.6 universal serial bus reset . . . . . . . . . . . . . . . . . . . . . . . 83 8.4.2.7 registers values after different resets . . . . . . . . . . . . . 84 8.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.5.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . 85 8.5.2 sim counter during stop mode recovery . . . . . . . . . . . . . . 85 8.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . . 85 8.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.6.2 interrupt status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.6.2.1 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . 90 8.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
system integration module (sim) technical data MC68HC08JB1 ? rev. 1.0 76 system integration module (sim) motorola 8.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.8.1 reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.2 introduction this section describes the system integration module (sim), which supports up to 8 external and/or internal interrupts. together with the cpu, the sim controls all mcu activities. the sim is a system state controller that coordinates cpu and exception timing. a block diagram of the sim is shown in figure 8-1 . figure 8-2 is a summary of the sim i/o registers. the sim is responsible for: bus clock generation and control for cpu and peripherals stop/wait/reset entry and recovery internal clock control master reset control, including power-on reset (por) and cop timeout interrupt control: acknowledge timing arbitration control timing vector address generation cpu enable/disable timing modular architecture expandable to 128 interrupt sources
system integration module (sim) introduction MC68HC08JB1 ? rev. 1.0 technical data motorola system integration module (sim) 77 figure 8-1. sim block diagram table 8-1. sim module signal name conventions signal name description oscxclk clock doubler output which has twice the frequency of osc1 from the oscillator oscout the oscxclk frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks. (bus clock = oscxclk ?4 = f osc ?2) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to oscillator) oscout (from clock doubler) internal clocks master reset control reset pin logic illegal opcode (from cpu) illegal address (from address map decoders) cop timeout (from cop module) interrupt sources cpu interface reset control sim counter cop clock oscxclk (from clock doubler) ?2 usb reset (from usb module) lvi reset (from lvi module) vdd internal pull-up
system integration module (sim) technical data MC68HC08JB1 ? rev. 1.0 78 system integration module (sim) motorola 8.3 sim bus clock control and generation the bus clock generator provides system clock signals for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, oscout, as shown in figure 8-3 . figure 8-3. sim clock signals 8.3.1 bus timing in user mode , the internal bus frequency is the oscillator frequency divided by two. 8.3.2 clock startup from por or lvi reset when the power-on reset (por) module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 oscxclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the ibus clocks start upon completion of the timeout. addr. register name bit 7 654321 bit 0 $fe01 reset status register (rsr) read: por pin cop ilop ilad usb lvi 0 write: por: 10000000 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write: rrrrrrrr reset: 00000000 figure 8-2. sim i/o register summary ?2 bus clock generators sim sim counter from clock doubler from clock doubler oscout oscxclk
system integration module (sim) reset and system initialization MC68HC08JB1 ? rev. 1.0 technical data motorola system integration module (sim) 79 8.3.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt or reset, the sim allows oscxclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 2048 oscxclk cycles. (see 8.7.2 stop mode .) in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 8.4 reset and system initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) illegal opcode illegal address universal serial bus module (usb) low-voltage inhibit module (lvi) all of these resets produce the vector $fffe?fff ($fefe?eff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 8.5 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the reset status register (rsr). (see 8.8 sim registers .)
system integration module (sim) technical data MC68HC08JB1 ? rev. 1.0 80 system integration module (sim) motorola 8.4.1 external pin reset the rst pin circuit includes an internal pullup device. pulling the asynchronous rst pin low halts all processing. the pin bit of the reset status register (rsr) is set as long as rst is held low for a minimum of 67 oscxclk cycles, assuming that neither the por nor the lvi was the source of the reset. see table 8-2 for details. figure 8-4 shows the relative timing. figure 8-4. external reset timing 8.4.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 oscxclk cycles to allow resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles. (see figure 8-5.) an internal reset can be caused by an illegal address, illegal opcode, cop timeout, lvi, the usb module or por. (see figure 8-6 . sources of internal reset .) note: for lvi or por resets, the sim cycles through 4096 oscxclk cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 8-5 . table 8-2. pin bit set timing reset type number of cycles required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l oscout
system integration module (sim) reset and system initialization MC68HC08JB1 ? rev. 1.0 technical data motorola system integration module (sim) 81 figure 8-5. internal reset timing the cop reset is asynchronous to the bus clock. figure 8-6. sources of internal reset the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. 8.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 oscxclk cycles. sixty-four oscxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the following events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscillator to drive oscxclk. internal clocks to the cpu and modules are held inactive for 4096 oscxclk cycles to allow stabilization of the oscillator. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high oscxclk illegal address rst illegal opcode rst coprst por internal reset lvi usb
system integration module (sim) technical data MC68HC08JB1 ? rev. 1.0 82 system integration module (sim) motorola the rst pin is driven low during the oscillator stabilization time. the por bit of the reset status register (rsr) is set and all other bits in the register are cleared. figure 8-7. por recovery 8.4.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the reset status register (rsr). the sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module timeout, write any value to location $ffff. writing to location $ffff clears the cop counter and stages 12 through 5 of the sim counter. the sim counter output, which occurs at least every 2 12 ?2 4 oscxclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. the cop module is disabled if the rst pin or the irq pin is held at v dd + v hi while the mcu is in monitor mode. the cop module can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq pin. this prevents the cop from becoming disabled as a result of external noise. porrst osc1 oscxclk oscout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff
system integration module (sim) reset and system initialization MC68HC08JB1 ? rev. 1.0 technical data motorola system integration module (sim) 83 8.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the reset status register (rsr) and causes a reset. if the stop enable bit, stop, in the mask option register is logic 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 8.4.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the reset status register (rsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. 8.4.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the lvi reset voltage, v trip . the lvi bit in the reset status register (rsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 oscxclk cycles. sixty-four oscxclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 8.4.2.6 universal serial bus reset the usb module will detect a reset signaled on the bus by the presence of an extended se0 at the usb data pins of a device. the mcu seeing a single-ended 0 on its usb data inputs for more than 2.5 m s treats that signal as a reset. after the reset is removed, the device will be in the attached, but not yet addressed or configured, state (refer to section 9.1 usb devices of the universal serial bus specification rev. 1.1). the device must be able to accept the device address via a set_address
system integration module (sim) technical data MC68HC08JB1 ? rev. 1.0 84 system integration module (sim) motorola command (refer to section 9.4 of the universal serial bus specification rev. 1.1) no later than 10ms after the reset is removed. usb reset can be disabled to generate an internal reset. it can be configured to generate irq1 interrupt. (see section 5. configuration register (config) .) note: usb reset is disabled when the usb module is disabled by clearing the usben bit of the usb address register (uaddr). 8.4.2.7 registers values after different resets some registers are reset by por or lvi reset only. table 8-3 shows the registers or register bits which are unaffected by normal resets. 8.5 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescalar for the computer operating properly module (cop). the sim counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of sim counters and supplies the clock for the cop module. the sim counter is clocked by the falling edge of oscxclk. table 8-3. registers not affected by normal reset bits registers after reset (except por or lvi) after por or lvi urstd, lvidis config unaffected 0 usben uaddr unaffected 0 pullen ucr3 unaffected 0 all usr0, usr1 unaffected indeterminate all ue0d0?e0d7 unaffected indeterminate all ue1d0?e1d7 unaffected indeterminate all ue2d0?e2d7 unaffected indeterminate all pta, ptc, ptd, and pte unaffected indeterminate ddra7 ddra unaffected 0
system integration module (sim) exception control MC68HC08JB1 ? rev. 1.0 technical data motorola system integration module (sim) 85 8.5.1 sim counter during power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the oscillator to drive the bus clock state machine. 8.5.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configuration register (config). if the ssrec bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 oscxclk cycles down to 2048 oscxclk cycles. this is ideal for applications using canned oscillators that do not require long startup times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared in the configuration register (config). 8.5.3 sim counter and reset states external reset has no effect on the sim counter. (see 8.7.2 stop mode for details.) the sim counter is free-running after all reset states. (see 8.4.2 active resets from internal sources for counter control and internal reset recovery sequences.) 8.6 exception control normal, sequential program execution can be changed in two different ways: interrupts maskable hardware cpu interrupts non-maskable software interrupt instruction (swi) reset
system integration module (sim) technical data MC68HC08JB1 ? rev. 1.0 86 system integration module (sim) motorola 8.6.1 interrupts an interrupt temporarily changes the sequence of program execution to respond to a particular event. figure 8-8 flow charts the handling of system interrupts. figure 8-8. interrupt processing no no no yes no yes no yes yes from reset i bit set? irq1 interrupt usb interrupt fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes i bit set? yes other interrupts no swi instruction rti instruction ? ? ? ? ?
system integration module (sim) exception control MC68HC08JB1 ? rev. 1.0 technical data motorola system integration module (sim) 87 interrupts are latched and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced or the i bit is cleared. at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 8-9 shows interrupt entry timing. figure 8-10 shows interrupt recovery timing. figure 8-9 . interrupt entry figure 8-10. interrupt recovery module idb r/w interrupt dummy sp sp ?1 sp ?2 sp ?3 sp ?4 vect h vect l start addr iab dummy pc ?1[7:0] pc ?1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ?4 sp ?3 sp ?2 sp ?1 sp pc pc + 1 iab ccr a x pc ?1 [7:0] pc ?1[15:8] opcode operand i bit
system integration module (sim) technical data MC68HC08JB1 ? rev. 1.0 88 system integration module (sim) motorola 8.6.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 8-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. figure 8-11 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine
system integration module (sim) exception control MC68HC08JB1 ? rev. 1.0 technical data motorola system integration module (sim) 89 8.6.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc?, as a hardware interrupt does. 8.6.2 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 8-4 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. table 8-4. interrupt sources source flags mask (1) int register flag priority (2) vector address swi instruction 0 $fffc?fffd usb reset interrupt rstf urstd if2 1 $fffa?fffb usb endpoint 0 transmit txd0f txd0ie usb endpoint 0 receive rxd0f rxd0ie usb endpoint 1transmit txd1f txd1ie usb endpoint 2 transmit txd2f txd2ie usb end of packet eopf eopie usb resume interrupt resumf irq1 interrupt (irq , pte4) irqf1 pte4if imask1 if1 2 $fff8?fff9 tim channel 0 ch0f ch0ie if3 3 $fff6?fff7 tim channel 1 ch1f ch1ie if4 4 $fff4?fff5 tim over?w tof toie if5 5 $fff2?fff3 keyboard pins keyf imaskk if6 6 $fff0?fff1 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. 2. 0 = highest priority
system integration module (sim) technical data MC68HC08JB1 ? rev. 1.0 90 system integration module (sim) motorola 8.6.2.1 interrupt status register 1 if6?f1 ?interrupt flags 1? these flags indicate the presence of interrupt requests from the sources shown in table 8-4 . 1 = interrupt request present 0 = no interrupt request present bit 0 and bit 1 ?always read 0 8.6.3 reset all reset sources always have equal and highest priority and cannot be arbitrated. 8.7 low-power modes executing the wait or stop instruction puts the mcu in a low-power- consumption mode for standby situations. the sim holds the cpu in a non-clocked state. the operation of each of these modes is described here. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 8.7.1 wait mode in wait mode, the cpu clocks are inactive while the peripheral clocks continue to run. figure 8-13 shows the timing for wait mode entry. address: $fe04 bit 7 654321 bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write: rrrrrrrr reset: 00000000 r = reserved figure 8-12. interrupt status register 1 (int1)
system integration module (sim) low-power modes MC68HC08JB1 ? rev. 1.0 technical data motorola system integration module (sim) 91 a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wait instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset. if the cop disable bit, copd, in the mask option register is logic 0, then the computer operating properly module (cop) is enabled and remains active in wait mode. figure 8-13. wait mode entry timing figure 8-14 and figure 8-15 show the timing for wait recovery. figure 8-14. wait recovery from interrupt wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt interrupt
system integration module (sim) technical data MC68HC08JB1 ? rev. 1.0 92 system integration module (sim) motorola figure 8-15. wait recovery from internal reset 8.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset also causes an exit from stop mode. the sim disables the oscillator signals (oscout and oscxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the configuration register (config). if ssrec is set, stop recovery is reduced from the normal delay of 4096 oscxclk cycles down to 2048. this is ideal for applications using canned oscillators that do not require long startup times from stop mode. note: external crystal applications should use the full stop recovery time by clearing the ssrec bit. the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 8-16 shows stop mode entry timing. note: to minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0. iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 oscxclk 32 cycles 32 cycles
system integration module (sim) sim registers MC68HC08JB1 ? rev. 1.0 technical data motorola system integration module (sim) 93 figure 8-16. stop mode entry timing figure 8-17. stop mode recovery from interrupt 8.8 sim registers the sim has one reset register. 8.8.1 reset status register this register contains seven flags that show the source of the last reset. all flag bits are cleared automatically following a read of the register. the register is initialized on power-up as shown with the por bit set and all other bits cleared. however, during a por or any other internal reset, the rst pin is pulled low. after the pin is released, it will be sampled 32 xclk cycles later. if the pin is not above a v ih at that time, then the pin bit in the rsr may be set in addition to whatever other bits are set. stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. oscxclk int iab stop + 2 stop + 2 sp sp ?1 sp ?2 sp ?3 stop +1 stop recovery period
system integration module (sim) technical data MC68HC08JB1 ? rev. 1.0 94 system integration module (sim) motorola por ?power-on reset bit 1 = a por has occurred 0 = read of rsr pin ?external reset bit 1 = an external reset has occurred since the last read of the rsr 0 = read of rsr cop ?computer operating properly reset bit 1 = a cop reset has occurred since the last read of the rsr 0 = por or read of rsr ilop ?illegal opcode reset bit an illegal opcode reset has occurred since the last read of the rsr 0 = por or read of rsr ilad ?illegal address reset bit (opcode fetches only) 1 = an illegal address reset has occurred since the last read of the rsr 0 = por or read of rsr usb ?universal serial bus reset bit 1 = last reset caused by the usb module 0 = por or read of rsr lvi ?low voltage inhibit reset bit 1 = a lvi reset has occurred since the last read of psr 0 = por or read of rsr address: $fe01 bit 7 654321 bit 0 read: por pin cop ilop ilad usb lvi 0 write: por: 10000000 = unimplemented figure 8-18. reset status register (rsr)
MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 95 technical data ?MC68HC08JB1 section 9. universal serial bus module (usb) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.5.1 usb protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.5.1.1 sync pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.5.1.2 packet identifier field . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.5.1.3 address field (addr) . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.5.1.4 endpoint field (endp). . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.5.1.5 cyclic redundancy check (crc) . . . . . . . . . . . . . . . . . 102 9.5.1.6 end-of-packet (eop) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.5.2 reset signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.5.3 suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.5.4 resume after suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.5.4.1 host initiated resume . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.5.4.2 usb reset signalling. . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.5.4.3 remote wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.5.5 low-speed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.6 clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.7 hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.7.1 voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.7.2 usb transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.7.2.1 output driver characteristics . . . . . . . . . . . . . . . . . . . . . 108 9.7.2.2 low speed (1.5 mbps) driver characteristics . . . . . . . . 108 9.7.2.3 receiver data jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.7.2.4 data source jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.7.2.5 data signal rise and fall time . . . . . . . . . . . . . . . . . . . 110
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 96 universal serial bus module (usb) motorola 9.7.3 usb control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.8 i/o register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.8.1 usb address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.8.2 usb interrupt register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.8.3 usb interrupt register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.8.4 usb interrupt register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.8.5 usb control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.8.6 usb control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.8.7 usb control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.8.8 usb control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.8.9 usb control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.8.10 usb status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.8.11 usb status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.8.12 usb endpoint 0 data registers . . . . . . . . . . . . . . . . . . . . . 130 9.8.13 usb endpoint 1 data registers . . . . . . . . . . . . . . . . . . . . . 131 9.8.14 usb endpoint 2 data registers . . . . . . . . . . . . . . . . . . . . . 132 9.9 usb interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.9.1 usb end-of-transaction interrupt . . . . . . . . . . . . . . . . . . . 133 9.9.1.1 receive control endpoint 0 . . . . . . . . . . . . . . . . . . . . . . 134 9.9.1.2 transmit control endpoint 0 . . . . . . . . . . . . . . . . . . . . . 136 9.9.1.3 transmit endpoint 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.9.1.4 transmit endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.9.2 resume interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.9.3 end-of-packet interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.2 introduction this section describes the universal serial bus (usb) module. the usb module is designed to serve as a low-speed (ls) usb device per the universal serial bus specification rev 1.1. control and interrupt data transfers are supported. endpoint 0 functions as a transmit/receive control endpoint; endpoint 1 functions as interrupt transmit endpoint; endpoint 2 functions as interrupt transmit endpoint.
universal serial bus module (usb) features MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 97 9.3 features features of the usb module include: full universal serial bus specification 1.1 low-speed functions 1.5 mbps data rate on-chip 3.3v regulator endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer endpoint 1 with 8-byte transmit buffer endpoint 2 with 8-byte transmit buffer usb data control logic: control endpoint 0 and interrupt endpoints 1 and 2 packet decoding/generation crc generation and checking nrzi (non-return-to zero inserted) encoding/decoding bit-stuffing usb reset options: internal mcu reset generation cpu interrupt request generation suspend and resume operations, with remote wakeup support usb-generated interrupts: transaction interrupt driven resume interrupt end-of-packet interrupt usb reset stall, nak, and ack handshake generation
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 98 universal serial bus module (usb) motorola 9.4 pin name conventions the usb share two i/o pins with two port e i/o pins. the full name of the usb i/o pin is listed in table 9-1 . the generic pin name appear in the text that follows. 9.5 functional description figure 9-1 shows the block diagram of the usb module. the usb module manages communications between the host and the usb function. the module is partitioned into three functional blocks. these blocks consist of a dual-function transceiver, the usb control logic, and the endpoint registers. the blocks are further detailed later in this section (see 9.7 hardware description ). figure 9-1. usb block diagram table 9-1. usb module pin name conventions usb generic pin names: d d+ full usb pin names: pte4/d pte3/d+ d + d transceiver rcv vpin vmin vpout vmout cpu bus usb registers usb upstream port usb control logic
universal serial bus module (usb) functional description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 99 9.5.1 usb protocol figure 9-2 shows the various transaction types supported by the usb module. the transactions are portrayed as error free. the effect of errors in the data flow are discussed later. figure 9-2. supported transaction types per endpoint setup in out data0/1 data0 data1 ack data1 out ack out data0 ack ack data0/1 endpoint 0 transactions: control write control read no-data control endpoints 1 & 2 transactions: interrupt bulk transmit in ack key: unrelated bus traffic host generated device generated ack setup out in data0/1 data0 data1 ack data1 in ack in data0 ack ack ack setup in data0 data1 ack ack data0/1 in ack
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 100 universal serial bus module (usb) motorola each usb transaction is comprised of a series of packets. the usb module supports the packet types shown in figure 9-3 . token packets are generated by the usb host and decoded by the usb device. data and handshake packets are both decoded and generated by the usb device, depending on the type of transaction. figure 9-3. supported usb packet types the following sections detail each segment used to form a complete usb transaction. 9.5.1.1 sync pattern the nrzi bit pattern shown in figure 9-4 is used as a synchronization pattern and is prefixed to each packet. this pattern is equivalent to a data pattern of seven 0s followed by a 1 ($80). figure 9-4. sync pattern token packet: in out sync pid pid addr endp crc5 eop setup data packet: data0 sync pid pid data crc16 eop data1 0 ?8 bytes handshake packet: ack nak sync pid pid eop stall sync pattern pid0 pid1 idle nrzi data encoding
universal serial bus module (usb) functional description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 101 the start of a packet (sop) is signaled by the originating port by driving the d+ and d?lines from the idle state (also referred to as the j state) to the opposite logic level (also referred to as the k state). this switch in levels represents the first bit of the sync field. figure 9-5 shows the data signaling and voltage levels for the start of packet and the sync pattern. figure 9-5. sop, sync signaling, and voltage levels 9.5.1.2 packet identifier field the packet identifier field is an 8-bit number comprised of the 4-bit packet identification and its complement. the field follows the sync pattern and determines the direction and type of transaction on the bus. table 9-2 shows the packet identifier values for the supported packet types. end of sync first bit of packet sop bus idle v oh (min.) v se (max) v se (min.) v ol (min.) v ss table 9-2. supported packet identi?rs packet identifier value packet identifier type %1001 in token %0001 out token %1101 setup token %0011 data0 packet %1011 data1 packet %0010 ack handshake %1010 nak handshake %1110 stall handshake
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 102 universal serial bus module (usb) motorola 9.5.1.3 address field (addr) the address field is a 7-bit number that is used to select a particular usb device. this field is compared to the lower seven bits of the uaddr register to determine if a given transaction is targeting the mcu usb device. 9.5.1.4 endpoint field (endp) the endpoint field is a 4-bit number that is used to select a particular endpoint within a usb device. for the mcu, this will be a binary number between 0 and 2 inclusive. any other value will cause the transaction to be ignored. 9.5.1.5 cyclic redundancy check (crc) cyclic redundancy checks are used to verify the address and data stream of a usb transaction. this field is five bits wide for token packets and 16 bits wide for data packets. crcs are generated in the transmitter and sent on the usb data lines after both the endpoint field and the data field. 9.5.1.6 end-of-packet (eop) the single-ended 0 (se0) state is used to signal an end-of-packet (eop). the single-ended 0 state is indicated by both d+ and d?being below 0.8 v. eop will be signaled by driving d+ and d?to the single-ended 0 state for two bit times followed by driving the lines to the idle state for one bit time. the transition from the single-ended 0 to the idle state defines the end of the packet. the idle state is asserted for one bit time and then both the d+ and d?output drivers are placed in their high-impedance state. the bus termination resistors hold the bus in the idle state. figure 9-6 shows the data signaling and voltage levels for an end-of-packet transaction.
universal serial bus module (usb) functional description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 103 figure 9-6. eop transaction voltage levels the width of the se0 in the eop is about two bit times. the eop width is measured with the same capacitive load used for maximum rise and fall times and is measured at the same level as the differential signal crossover points of the data lines. figure 9-7. eop width timing 9.5.2 reset signaling the usb module will detect a reset signaled on the bus by the presence of an extended se0 at the usb data pins of a device. the mcu seeing a single-ended 0 on its usb data inputs for more than 8 m s treats that signal as a reset. a usb sourced reset will hold the mcu in reset for the duration of the reset on the usb bus. the usb bit in the reset status register (rsr) will be set after the internal reset is removed. refer to 8.8.1 reset status register for more detail. the mcu? reset recovery sequence is detailed in section 8. system integration module (sim) . bus driven to last bit of bus idle eop strobe packet idle state bus floats v oh (min.) v se (max) v se (min.) v ol (min.) v ss eop width t period differential data lines data crossover level
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 104 universal serial bus module (usb) motorola the reset flag bit (rstf) in the usb interrupt register 1 (uir1) also will be set after the internal reset is removed. refer to 9.8.3 usb interrupt register 1 for more detail. after a reset is removed, the device will be in the default, but not yet addressed or configured state (refer to section 9.1 usb device states of the universal serial bus specification rev. 1.1 ). the device must be able to accept a device address via a set_address command (refer to section 9.4 standard device request in the universal serial bus specification rev. 1.1 ) no later than 10 ms after the reset is removed. reset can wake a device from the suspended mode. note: usb reset can be configured not to generate a reset signal to the cpu by setting the urstd bit of the configuration register (see section 5. configuration register (config) ) . when a usb reset is detected, the cpu generates an usb interrupt. 9.5.3 suspend the mcu supports suspend mode for low power. suspend mode should be entered when the usb data lines are in the idle state for more than 3.0 ms. entry into suspend mode is controlled by the suspnd bit in the usb interrupt register. any low-speed bus activity should keep the device out of the suspend state. low-speed devices are kept awake by periodic low-speed eop signals from the host. this is referred to as low speed keep alive (refer to section 11.8.4.1 low-speed keep-alive in the universal serial bus specification rev. 1.1 ). firmware should monitor the eopf flag and enter suspend mode by setting the suspnd bit if an eop is not detected for 3 ms. per the usb specification, the bus powered usb system is required to draw less than 500 m a from the v dd supply when in the suspend state. this includes the current supplied by the voltage regulator to the 1.5k w to ground termination resistors placed at the host end of the usb bus. this low-current requirement means that firmware is responsible for entering stop mode once the usb module has been placed in the suspend state.
universal serial bus module (usb) functional description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 105 9.5.4 resume after suspend the mcu can be activated from the suspend state by normal bus activity, a usb reset signal, or by a forced resume driven from the mcu. 9.5.4.1 host initiated resume the host signals resume by initiating resume signalling (k state) for at least 20ms followed by a standard low-speed eop signal. this 20ms ensures that all devices in the usb network are awakened. after resuming the bus, the host must begin sending bus traffic within 3ms to prevent the device from re-entering suspend mode. 9.5.4.2 usb reset signalling reset can wake a device from the suspended mode. 9.5.4.3 remote wakeup the mcu also supports the remote wakeup feature. the firmware has the ability to exit suspend mode by signaling a resume state to the upstream host or hub. a non-idle state (k state) on the usb data lines is accomplished by asserting the fresum bit in the ucr1 register. when using the remote wakeup capability, the firmware must wait for at least 5ms after the bus is in the idle state before sending the remote wakeup resume signaling. this allows the upstream devices to get into their suspend state and prepare for propagating resume signaling. the fresum bit should be asserted to cause the resume state on the usb data lines for at least 10ms, but not more than 15ms. note that the resume signalling is controlled by the fresum bit and meeting the timing specifications is dependent on the firmware. when fresum is cleared by firmware, the data lines will return to their high-impedance state. refer to the register definitions (see 9.8.6 usb control register 1 ) for more information about how the force resume (fresum) bit can be used to initiate the remote wakeup feature.
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 106 universal serial bus module (usb) motorola 9.5.5 low-speed device low-speed devices are configured by the position of a pull-up resistor on the usb d?pin of the mcu. low-speed devices are terminated as shown in figure 9-8 with the pull-up on the d?line. figure 9-8. external low-speed device configuration for low-speed transmissions, the transmitter? eop width must be between 1.25 m s and 1.50 m s. these ranges include timing variations due to differential buffer delay and rise/fall time mismatches and to noise and other random effects. a low-speed receiver must accept a 670ns se0 followed by a j transition as a valid eop. an se0 shorter than 330ns or an se0 not followed by a j transition are rejected as an eop. any se0 that is 8 m s or longer is automatically a reset. 9.6 clock requirements the low-speed data rate is nominally 1.5mbps. the oscxclk signal driven by the oscillator circuits is the clock source for the usb module and requires that a 6mhz oscillator circuit be connected to the osc1 and osc2 pins. the permitted frequency tolerance for low-speed functions is approximately 1.5% (15,000 ppm). this tolerance includes inaccuracies from all sources: initial frequency accuracy, crystal capacitive loading, supply voltage on the oscillator, temperature, and aging. the jitter in the low-speed data rate must be less than 10ns. 1.5 k w d+ d v reg (3.3 v) usb low-speed cable mcu
universal serial bus module (usb) hardware description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 107 9.7 hardware description the usb module as previously shown in figure 9-1 contains three functional blocks: a low-speed usb transceiver, the usb control logic, and the usb registers. the following details the function of the regulator, transceiver, and control logic. see 9.8 i/o register description for the register discussion. 9.7.1 voltage regulator the usb data lines are required by the usb specification to have an output voltage between 2.8 v and 3.6 v. the data lines also are required to have an external 1.5k w pull-up resistor connected between a data line and a voltage source between 3.0 v and 3.6 v. figure 9-9 shows the worst case electrical connection for the voltage regulator. figure 9-9. regulator electrical connections 9.7.2 usb transceiver the usb transceiver provides the physical interface to the usb d+ and d?data lines. the transceiver is composed of two parts: an output drive circuit and a receiver. r1 d+ d usb cable low-speed transceiver r2 r2 host or hub 3.3 v regulator 4.0 v ?5.5 v usb data lines r1 = 1.5 k w 5% r2 = 15 k w 5%
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 108 universal serial bus module (usb) motorola 9.7.2.1 output driver characteristics the usb transceiver uses a differential output driver to drive the usb data signal onto the usb cable. the static output swing of the driver in its low state is below the v ol of 0.3v with a 1.5k w load to 3.6v and in its high state is above the v oh of 2.8 v with a 15k w load to ground. the output swings between the differential high and low state are well balanced to minimize signal skew. slew rate control on the driver is used to minimize the radiated noise and cross talk. the driver? outputs support 3-state operation to achieve bidirectional half duplex operation. the driver can tolerate a voltage on the signal pins of ?.0v to 5.5v with respect to local ground reference without damage. 9.7.2.2 low speed (1.5 mbps) driver characteristics the rise and fall time of the signals on this cable are greater than 75 ns and less than 300 ns. the edges are matched to within 20% to minimize rfi emissions and signal skew. usb data transmission is done with differential signals. a differential input receiver is used to accept the usb data signal. a differential 1 on the bus is represented by d+ being at least 200mv more positive than d?as seen at the receiver, and a differential 0 is represented by d? being at least 200mv more positive than d+ as seen at the receiver. the signal cross over point must be between 1.3v and 2.0v. figure 9-10. receiver characteristics one bit time (1.5 mb/s) signal pins pass output spec levels with minimal reflections and ringing v se (min.) v se (max) v ss
universal serial bus module (usb) hardware description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 109 the receiver features an input sensitivity of 200mv when both differential data inputs are in the differential common mode range of 0.8v to 2.5v as shown in figure 9-11 . in addition to the differential receiver, there is a single-ended receiver (schmitt trigger) for each of the two data lines. figure 9-11. differential input sensitivity range 9.7.2.3 receiver data jitter the data receivers for all types of devices must be able to properly decode the differential data in the presence of jitter. the more of the bit time that any data edge can occupy and still be decoded, the more reliable the data transfer will be. data receivers are required to decode differential data transitions that occur in a window plus and minus a nominal quarter bit time from the nominal (centered) data edge position. jitter will be caused by the delay mismatches and by mismatches in the source and destination data rates (frequencies). the receive data jitter budget for low speed is given in section 16. electrical specifications . the specification includes the consecutive (next) and paired transition values for each source of jitter. 9.7.2.4 data source jitter the source of data can have some variation (jitter) in the timing of edges of the data transmitted. the time between any set of data transitions is n t period jitter time, where n is the number of bits between the transitions and t period is defined as the actual period of the data rate. the data jitter is measured with the same capacitive load used for maximum rise and fall times and is measured at the crossover points of the data lines as shown in figure 9-12 . differential output crossover voltage range differential input voltage range input voltage range (volts) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 ?.0 5.5
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 110 universal serial bus module (usb) motorola figure 9-12. data jitter for low-speed transmissions, the jitter time for any consecutive differential data transitions must be within 25ns and within 10ns for any set of paired differential data transitions. these jitter numbers include timing variations due to differential buffer delay, rise/fall time mismatches, internal clock source jitter, noise and other random effects. 9.7.2.5 data signal rise and fall time the output rise time and fall time are measured between 10% and 90% of the signal. edge transition time for the rising and falling edges of low-speed signals is 75ns (minimum) into a capacitive load (c l ) of 200pf and 300ns (maximum) into a capacitive load of 600pf. the rising and falling edges should be transitioning (monotonic) smoothly when driving the cable to avoid excessive emi. figure 9-13. data signal rise and fall time consecutive transitions t period differential data lines crossover points paired transitions jitter t r differential data lines t f rise time fall time 10% 90% 90% 10% low speed: 75 ns at c l = 200 pf, 300 ns at c l = 600 pf c l c l + +
universal serial bus module (usb) i/o register description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 111 9.7.3 usb control logic the usb control logic manages data movement between the cpu and the transceiver. the control logic handles both transmit and receive operations on the usb. it contains the logic used to manipulate the transceiver and the endpoint registers. the byte count buffer is loaded with the active transmit endpoints byte count value during transmit operations. this same buffer is used for receive transactions to count the number of bytes received and, upon the end of the transaction, transfer that number to the receive endpoints byte count register. when transmitting, the control logic handles parallel-to-serial conversion, crc generation, nrzi encoding, and bit stuffing. when receiving, the control logic handles sync detection, packet identification, end-of-packet detection, bit (un)stuffing, nrzi decoding, crc validation, and serial-to-parallel conversion. errors detected by the control logic include bad crc, timeout while waiting for eop, and bit stuffing violations. 9.8 i/o register description the usb endpoint registers are comprised of a set of control/status registers and 24 data registers that provide storage for the buffering of data between usb and the cpu. see figure 9-14 . addr. register name bit 7 654321 bit 0 $0018 usb interrupt register 2 (uir2) read: 00000000 write: eopfr rstfr txd2fr txd1fr resumfr txd0fr rxd0fr reset: 00000000 $0019 usb control register 2 (ucr2) read: t2seq stall2 tx2e 0 tp2siz3 tp2siz2 tp2siz1 tp2siz0 write: reset: 00000000 = unimplemented u = unaffected by reset figure 9-14. usb i/o register summary (sheet 1 of 5)
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 112 universal serial bus module (usb) motorola $001a usb control register 3 (ucr3) read: tx1st 0 ostall0 istall0 0 pullen enable2 enable1 write: tx1str reset: 000000*00 *note: pullen bit is reset by por or lvi reset only. $001b usb control register 4 (ucr4) read: 00000 fusbo fdp fdm write: reset: 00000000 $0020 usb endpoint 0 data register 0 (ue0d0) read: ue0r07 ue0r06 ue0r05 ue0r04 ue0r03 ue0r02 ue0r01 ue0r00 write: ue0t07 ue0t06 ue0t05 ue0t04 ue0t03 ue0t02 ue0t01 ue0t00 reset: unaffected by reset $0021 usb endpoint 0 data register 1 (ue0d1) read: ue0r17 ue0r16 ue0r15 ue0r14 ue0r13 ue0r12 ue0r11 ue0r10 write: ue0t17 ue0t16 ue0t15 ue0t14 ue0t13 ue0t12 ue0t11 ue0t10 reset: unaffected by reset $0022 usb endpoint 0 data register 2 (ue0d2) read: ue0r27 ue0r26 ue0r25 ue0r24 ue0r23 ue0r22 ue0r21 ue0r20 write: ue0t27 ue0t26 ue0t25 ue0t24 ue0t23 ue0t22 ue0t21 ue0t20 reset: unaffected by reset $0023 usb endpoint 0 data register 3 (ue0d3) read: ue0r37 ue0r36 ue0r35 ue0r34 ue0r33 ue0r32 ue0r31 ue0r30 write: ue0t37 ue0t36 ue0t35 ue0t34 ue0t33 ue0t32 ue0t31 ue0t30 reset: unaffected by reset $0024 usb endpoint 0 data register 4 (ue0d4) read: ue0r47 ue0r46 ue0r45 ue0r44 ue0r43 ue0r42 ue0r41 ue0r40 write: ue0t47 ue0t46 ue0t45 ue0t44 ue0t43 ue0t42 ue0t41 ue0t40 reset: unaffected by reset $0025 usb endpoint 0 data register 5 (ue0d5) read: ue0r57 ue0r56 ue0r55 ue0r54 ue0r53 ue0r52 ue0r51 ue0r50 write: ue0t57 ue0t56 ue0t55 ue0t54 ue0t53 ue0t52 ue0t51 ue0t50 reset: unaffected by reset $0026 usb endpoint 0 data register 6 (ue0d6) read: ue0r67 ue0r66 ue0r65 ue0r64 ue0r63 ue0r62 ue0r61 ue0r60 write: ue0t67 ue0t66 ue0t65 ue0t64 ue0t63 ue0t62 ue0t61 ue0t60 reset: unaffected by reset $0027 usb endpoint 0 data register 7 (ue0d7) read: ue0r77 ue0r76 ue0r75 ue0r74 ue0r73 ue0r72 ue0r71 ue0r70 write: ue0t77 ue0t76 ue0t75 ue0t74 ue0t73 ue0t72 ue0t71 ue0t70 reset: unaffected by reset addr. register name bit 7 654321 bit 0 = unimplemented u = unaffected by reset figure 9-14. usb i/o register summary (sheet 2 of 5)
universal serial bus module (usb) i/o register description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 113 $0028 usb endpoint 1 data register 0 (ue1d0) read: write: ue1t07 ue1t06 ue1t05 ue1t04 ue1t03 ue1t02 ue1t01 ue1t00 reset: unaffected by reset $0029 usb endpoint 1 data register 1 (ue1d1) read: write: ue1t17 ue1t16 ue1t15 ue1t14 ue1t13 ue1t12 ue1t11 ue1t10 reset: unaffected by reset $002a usb endpoint 1 data register 2 (ue1d2) read: write: ue1t27 ue1t26 ue1t25 ue1t24 ue1t23 ue1t22 ue1t21 ue1t20 reset: unaffected by reset $002b usb endpoint 1 data register 3 (ue1d3) read: write: ue1t37 ue1t36 ue1t35 ue1t34 ue1t33 ue1t32 ue1t31 ue1t30 reset: unaffected by reset $002c usb endpoint 1 data register 4 (ue1d4) read: write: ue1t47 ue1t46 ue1t45 ue1t44 ue1t43 ue1t42 ue1t41 ue1t40 reset: unaffected by reset $002d usb endpoint 1 data register5 (ue1d5) read: write: ue1t57 ue1t56 ue1t55 ue1t54 ue1t53 ue1t52 ue1t51 ue1t50 reset: unaffected by reset $002e usb endpoint 1 data register 6 (ue1d6) read: write: ue1t67 ue1t66 ue1t65 ue1t64 ue1t63 ue1t62 ue1t61 ue1t60 reset: unaffected by reset $002f usb endpoint 1 data register 7 (ue1d7) read: write: ue1t77 ue1t76 ue1t75 ue1t74 ue1t73 ue1t72 ue1t71 ue1t70 reset: unaffected by reset $0030 usb endpoint 2 data register 0 (ue2d0) read: write: ue2t07 ue2t06 ue2t05 ue2t04 ue2t03 ue2t02 ue2t01 ue2t00 reset: unaffected by reset $0031 usb endpoint 2 data register 1 (ue2d1) read: write: ue2t17 ue2t16 ue2t15 ue2t14 ue2t13 ue2t12 ue2t11 ue2t10 reset: unaffected by reset addr. register name bit 7 654321 bit 0 = unimplemented u = unaffected by reset figure 9-14. usb i/o register summary (sheet 3 of 5)
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 114 universal serial bus module (usb) motorola $0032 usb endpoint 2 data register 2 (ue2d2) read: write: ue2t27 ue2t26 ue2t25 ue2t24 ue2t23 ue2t22 ue2t21 ue2t20 reset: unaffected by reset $0033 usb endpoint 2 data register 3 (ue2d3) read: write: ue2t37 ue2t36 ue2t35 ue2t34 ue2t33 ue2t32 ue2t31 ue2t30 reset: unaffected by reset $0034 usb endpoint 2 data register 4 (ue2d4) read: write: ue2t47 ue2t46 ue2t45 ue2t44 ue2t43 ue2t42 ue2t41 ue2t40 reset: unaffected by reset $0035 usb endpoint 2 data register 5 (ue2d5) read: write: ue2t57 ue2t56 ue2t55 ue2t54 ue2t53 ue2t52 ue2t51 ue2t50 reset: unaffected by reset $0036 usb endpoint 2 data register 6 (ue2d6) read: write: ue2t67 ue2t66 ue2t65 ue2t64 ue2t63 ue2t62 ue2t61 ue2t60 reset: unaffected by reset $0037 usb endpoint 2 data register 7 (ue2d7) read: write: ue2t77 ue2t76 ue2t75 ue2t74 ue2t73 ue2t72 ue2t71 ue2t70 reset: unaffected by reset $0038 usb address register (uaddr) read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset: 00000000 note: usben bit is reset by por or lvi reset only. $0039 usb interrupt register 0 (uir0) read: eopie suspnd txd2ie 0 txd1ie 0 txd0ie rxd0ie write: reset: 00000000 $003a usb interrupt register 1 (uir1) read: eopf rstf txd2f 0 txd1f resumf txd0f rxd0f write: reset: 00000000 $003b usb control register 0 (ucr0) read: t0seq 0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset: 00000000 addr. register name bit 7 654321 bit 0 = unimplemented u = unaffected by reset figure 9-14. usb i/o register summary (sheet 4 of 5)
universal serial bus module (usb) i/o register description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 115 9.8.1 usb address register usben ?usb module enable this read/write bit enables and disables the usb module and the usb pins. when usben is set, the usb module is enabled and the pte4 interrupt is disabled. when usben is clear, the usb module will not respond to any tokens, usb reset and usb related interrupts are disabled, and pins pte4/d?and pte3/d+ function as high current open-drain i/o port pins pte4 and pte3. 1 = usb function enabled and pte4 interrupt is disabled 0 = usb function disabled including usb interrupt, reset and reset interrupt uadd6?add0 ?usb function address these bits specify the usb address of the device. reset clears these bits. $003c usb control register 1 (ucr1) read: t1seq stall1 tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset: 00000000 $003d usb status register 0 (usr0) read: r0seq setup 0 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: reset: unaffected by reset $003e usb status register 1 (usr1) read: 0 txack txnak txstl 0000 write: reset: 00000000 address: $0038 bit 7 654321 bit 0 read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset: 0*0000000 note: usben bit is reset by por or lvi reset only. figure 9-15. usb address register (uaddr) addr. register name bit 7 654321 bit 0 = unimplemented u = unaffected by reset figure 9-14. usb i/o register summary (sheet 5 of 5)
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 116 universal serial bus module (usb) motorola 9.8.2 usb interrupt register 0 eopie ?end-of-packet detect interrupt enable this read/write bit enables the usb to generate cpu interrupt requests when the eopf bit becomes set. reset clears the eopie bit. 1 = end-of-packet sequence detection can generate a cpu interrupt request 0 = end-of-packet sequence detection cannot generate a cpu interrupt request suspnd ?usb suspend bit to save power, this read/write bit should be set by the software if a 3-ms constant idle state is detected on the usb bus. setting this bit puts the transceiver into a power-saving mode. the resumf flag must be cleared before setting suspnd. software must clear this bit after the resume flag (resumf) is set while this resume interrupt flag is serviced. txd2ie ?endpoint 2 transmit interrupt enable this read/write bit enables the transmit endpoint 2 to generate cpu interrupt requests when the txd2f bit becomes set. reset clears the txd2ie bit. 1 = transmit endpoint 2 can generate a cpu interrupt request 0 = transmit endpoint 2 cannot generate a cpu interrupt request address: $0039 bit 7 654321 bit 0 read: eopie suspnd txd2ie 0 txd1ie 0 txd0ie rxd0ie write: reset: 00000000 = unimplemented figure 9-16. usb interrupt register 0 (uir0)
universal serial bus module (usb) i/o register description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 117 txd1ie ?endpoint 1 transmit interrupt enable this read/write bit enables the transmit endpoint 1 to generate cpu interrupt requests when the txd1f bit becomes set. reset clears the txd1ie bit. 1 = transmit endpoints 1 can generate a cpu interrupt request 0 = transmit endpoints 1 cannot generate a cpu interrupt request txd0ie ?endpoint 0 transmit interrupt enable this read/write bit enables the transmit endpoint 0 to generate cpu interrupt requests when the txd0f bit becomes set. reset clears the txd0ie bit. 1 = transmit endpoint 0 can generate a cpu interrupt request 0 = transmit endpoint 0 cannot generate a cpu interrupt request rxd0ie ?endpoint 0 receive interrupt enable this read/write bit enables the receive endpoint 0 to generate cpu interrupt requests when the rxd0f bit becomes set. reset clears the rxd0ie bit. 1 = receive endpoint 0 can generate a cpu interrupt request 0 = receive endpoint 0 cannot generate a cpu interrupt request 9.8.3 usb interrupt register 1 eopf ?end-of-packet detect flag this read-only bit is set when a valid end-of-packet sequence is detected on the d+ and d?lines. software must clear this flag by writing a logic 1 to the eopfr bit. reset clears this bit. writing to eopf has no effect. 1 = end-of-packet sequence has been detected 0 = end-of-packet sequence has not been detected address: $003a bit 7 654321 bit 0 read: eopf rstf txd2f 0 txd1f resumf txd0f rxd0f write: reset: 00000000 = unimplemented figure 9-17. usb interrupt register 1 (uir1)
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 118 universal serial bus module (usb) motorola rstf ?usb reset flag this read-only bit is set when a valid reset signal state is detected on the d+ and d?lines. if the urstd bit of the configuration register (config) is clear, this reset detection will generate an internal reset signal to reset the cpu and other peripherals including the usb module. if the urstd bit is set, this reset detection will generate an usb interrupt. this bit is cleared by writing a logic 1 to the rstfr bit. this bit also is cleared by a por reset. note: the usb bit in the rsr register (see 8.8.1 reset status register ) is also a usb reset indicator. txd2f ?endpoint 2 data transmit flag this read-only bit is set after the data stored in endpoint 2 transmit buffers has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the txd2fr bit. to enable the next data packet transmission, tx2e also must be set. if the txd2f bit is not cleared, a nak handshake will be returned in the next in transaction. reset clears this bit. writing to txd2f has no effect. 1 = transmit on endpoint 2 has occurred 0 = transmit on endpoint 2 has not occurred txd1f ?endpoint 1 data transmit flag this read-only bit is set after the data stored in the endpoint 1 transmit buffer has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the txd1fr bit. to enable the next data packet transmission, tx1e also must be set. if the txd1f bit is not cleared, a nak handshake will be returned in the next in transaction. reset clears this bit. writing to txd1f has no effect. 1 = transmit on endpoint 1has occurred 0 = transmit on endpoint 1has not occurred
universal serial bus module (usb) i/o register description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 119 resumf ?resume flag this read-only bit is set when usb bus activity is detected while the suspnd bit is set. software must clear this flag by writing a logic 1 to the resumfr bit. reset clears this bit. writing a logic 0 to resumf has no effect. 1 = usb bus activity has been detected 0 = no usb bus activity has been detected txd0f ?endpoint 0 data transmit flag this read-only bit is set after the data stored in endpoint 0 transmit buffers has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the txd0fr bit. to enable the next data packet transmission, tx0e also must be set. if the txd0f bit is not cleared, a nak handshake will be returned in the next in transaction. reset clears this bit. writing to txd0f has no effect. 1 = transmit on endpoint 0 has occurred 0 = transmit on endpoint 0 has not occurred rxd0f ?endpoint 0 data receive flag this read-only bit is set after the usb module has received a data packet and responded with an ack handshake packet. software must clear this flag by writing a logic 1 to the rxd0fr bit after all of the received data has been read. software also must set the rx0e bit to 1 to enable the next data packet reception. if the rxd0f bit is not cleared, the usb will respond with a nak handshake to any endpoint 0 out tokens; but does not respond to a setup token. reset clears this bit. writing to rxd0f has no effect. 1 = receive on endpoint 0 has occurred 0 = receive on endpoint 0 has not occurred
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 120 universal serial bus module (usb) motorola 9.8.4 usb interrupt register 2 eopfr ?end-of-packet flag reset writing a logic 1 to this write-only bit will clear the eopf bit if it is set. writing a logic 0 to the eopfr has no effect. reset clears this bit. rstfr ?clear reset indicator bit writing a logic 1 to this write-only bit will clear the rstf bit if it is set. writing a logic 0 to the rstfr has no effect. reset clears this bit. txd2fr ?endpoint 2 transmit flag reset writing a logic 1 to this write-only bit will clear the txd2f bit if it is set. writing a logic 0 to txd2fr has no effect. reset clears this bit. txd1fr ?endpoint 1 transmit flag reset writing a logic 1 to this write-only bit will clear the txd1f bit if it is set. writing a logic 0 to txd1fr has no effect. reset clears this bit. resumfr ?resume flag reset writing a logic 1 to this write-only bit will clear the resumf bit if it is set. writing to resumfr has no effect. reset clears this bit. txd0fr ?endpoint 0 transmit flag reset writing a logic 1 to this write-only bit will clear the txd0f bit if it is set. writing a logic 0 to txd0fr has no effect. reset clears this bit. rxd0fr ?endpoint 0 receive flag reset writing a logic 1 to this write-only bit will clear the rxd0f bit if it is set. writing a logic 0 to rxd0fr has no effect. reset clears this bit. address: $0018 bit 7 654321 bit 0 read: 00 00 0 0 0 0 write: eopfr rstfr txd2fr txd1fr resumfr txd0fr rxd0fr reset: 00000000 figure 9-18. usb interrupt register 2 (uir2)
universal serial bus module (usb) i/o register description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 121 9.8.5 usb control register 0 t0seq ?endpoint 0 transmit sequence bit this read/write bit determines which type of data packet (data0 or data1) will be sent during the next in transaction directed at endpoint 0. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active for next endpoint 0 transmit 0 = data0 token active for next endpoint 0 transmit tx0e ?endpoint 0 transmit enable this read/write bit enables a transmit to occur when the usb host controller sends an in token to endpoint 0. software should set this bit when data is ready to be transmitted. it must be cleared by software when no more endpoint 0 data needs to be transmitted. if this bit is 0 or the txd0f is set, the usb will respond with a nak handshake to any endpoint 0 in tokens. reset clears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak rx0e ?endpoint 0 receive enable this read/write bit enables a receive to occur when the usb host controller sends an out token to endpoint 0. software should set this bit when data is ready to be received. it must be cleared by software when data cannot be received. if this bit is 0 or the rxd0f is set, the usb will respond with a nak handshake to any endpoint 0 out tokens; but does not respond to a setup token. reset clears this bit. 1 = data is ready to be received 0 = not ready for data. respond with nak address: $003b bit 7 654321 bit 0 read: t0seq 0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset: 00000000 figure 9-19. usb control register 0 (ucr0)
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 122 universal serial bus module (usb) motorola tp0siz3?p0siz0 ?endpoint 0 transmit data packet size these read/write bits store the number of transmit data bytes for the next in token request for endpoint 0. these bits are cleared by reset. 9.8.6 usb control register 1 t1seq ?endpoint 1 transmit sequence bit this read/write bit determines which type of data packet (data0 or data1) will be sent during the next in transaction directed to endpoint 1. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active for next endpoint 1 transmit 0 = data0 token active for next endpoint 1 transmit stall1 ?endpoint 1 force stall bit this read/write bit causes endpoint 1 to return a stall handshake when polled by either an in or out token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default tx1e ?endpoint 1 transmit enable this read/write bit enables a transmit to occur when the usb host controller sends an in token to endpoint 1. the appropriate endpoint enable bit, enable1 bit in the ucr3 register, also should be set. software should set the tx1e bit when data is ready to be transmitted. it must be cleared by software when no more data needs to be transmitted. address: $003c bit 7 654321 bit 0 read: t1seq stall1 tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset: 00000000 figure 9-20. usb control register 1 (ucr1)
universal serial bus module (usb) i/o register description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 123 if this bit is 0 or the txd1f is set, the usb will respond with a nak handshake to any endpoint 1 directed in tokens. reset clears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak fresum ?force resume this read/write bit forces a resume state (k or non-idle state) onto the usb data lines to initiate a remote wakeup. software should control the timing of the forced resume to be between 10 and 15 ms. setting this bit will not cause the resumf bit to be set. 1 = force data lines to k state 0 = default tp1siz3?p1siz0 ?endpoint 1 transmit data packet size these read/write bits store the number of transmit data bytes for the next in token request for endpoint 1. these bits are cleared by reset. 9.8.7 usb control register 2 t2seq ?endpoint 2 transmit sequence bit this read/write bit determines which type of data packet (data0 or data1) will be sent during the next in transaction directed to endpoint 2. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active for next endpoint 2 transmit 0 = data0 token active for next endpoint 2 transmit address: $0019 bit 7 654321 bit 0 read: t2seq stall2 tx2e 0 tp2siz3 tp2siz2 tp2siz1 tp2siz0 write: reset: 00000000 figure 9-21. usb control register 2 (ucr2)
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 124 universal serial bus module (usb) motorola stall2 ?endpoint 2 force stall bit this read/write bit causes endpoint 2 to return a stall handshake when polled by either an in or out token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default tx2e ?endpoint 2 transmit enable this read/write bit enables a transmit to occur when the usb host controller sends an in token to endpoint 2. the appropriate endpoint enable bit, enable2 bit in the ucr3 register, also should be set. software should set the tx2e bit when data is ready to be transmitted. it must be cleared by software when no more data needs to be transmitted. if this bit is 0 or the txd2f is set, the usb will respond with a nak handshake to any endpoint 2 directed in tokens. reset clears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak tp2siz3?p2siz0 ?endpoint 2 transmit data packet size these read/write bits store the number of transmit data bytes for the next in token request for endpoint 2. these bits are cleared by reset.
universal serial bus module (usb) i/o register description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 125 9.8.8 usb control register 3 tx1st ?endpoint 0 transmit first flag this read-only bit is set if the endpoint 0 data transmit flag (txd0f) is set when the usb control logic is setting the endpoint 0 data receive flag (rxd0f). in other words, if an unserviced endpoint 0 transmit flag is still set at the end of an endpoint 0 reception, then this bit will be set. this bit lets the firmware know that the endpoint 0 transmission happened before the endpoint 0 reception. reset clears this bit. 1 = in transaction occurred before setup/out 0 = in transaction occurred after setup/out tx1str ?clear endpoint 0 transmit first flag writing a logic 1 to this write-only bit will clear the tx1st bit if it is set. writing a logic 0 to the tx1str has no effect. reset clears this bit. ostall0 ?endpoint 0 force stall bit for out token this read/write bit causes endpoint 0 to return a stall handshake when polled by an out token by the usb host controller. the usb hardware clears this bit when a setup token is received. reset clears this bit. 1 = send stall handshake 0 = default address: $001a bit 7 654321 bit 0 read: tx1st 0 ostall0 istall0 0 pullen enable2 enable1 write: tx1str reset: 000000*00 = unimplemented note: pullen bit is reset by por or lvi reset only. figure 9-22. usb control register 3 (ucr3)
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 126 universal serial bus module (usb) motorola istall0 ?endpoint 0 force stall bit for in token this read/write bit causes endpoint 0 to return a stall handshake when polled by an in token by the usb host controller. the usb hardware clears this bit when a setup token is received. reset clears this bit. 1 = send stall handshake 0 = default pullen ?pull-up enable this read/write bit controls the pull-up option for the usb d?pin if the usb module is enabled. 1 = configure d?pin to have internal pull-up 0 = disconnect d?pin internal pull-up enable2 ?endpoint 2 enable this read/write bit enables endpoint 2 and allows the usb to respond to in packets addressed to endpoint 2. reset clears this bit. 1 = endpoint 2 is enabled and can respond to an in token 0 = endpoint 2 is disabled enable1 ?endpoint 1 enable this read/write bit enables endpoint 1 and allows the usb to respond to in packets addressed to endpoint 1. reset clears this bit. 1 = endpoint 1 is enabled and can respond to an in token 0 = endpoint 1 is disabled
universal serial bus module (usb) i/o register description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 127 9.8.9 usb control register 4 usb control register 4 directly controls the usb data pins d+ and d? if the fusbo bit, and the usben bit of the usb address register (uaddr) are set, the output buffers of the usb modules are enabled and the corresponding levels of the usb data pins d+ and d?are equal to the values set by the fdp and the fdm bits. fusbo ?force usb output this read/write bit enables the usb output buffers. 1 = enables usb output buffers 0 = usb module in normal operation fdp ?force d+ this read/write bit determinates the output level of d+. 1 = d+ at output high level 0 = d+ at output low level fdm ?force d this read/write bit determinates the output level of d? 1 = d?at output high level 0 = d?at output low level note: customers must be very careful when setting the ucr4 register. when the fusbo and the usben bits are set, the usb module is in output mode and it will not recognize any usb signals including the usb reset signal. the ucr4 register is used for some special applications. customers are not normally expected to use this register. address: $001b bit 7 654321 bit 0 read: 0 0 0 0 0 fusbo fdp fdm write: reset: 00000000 = unimplemented figure 9-23. usb control register 4 (ucr4)
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 128 universal serial bus module (usb) motorola 9.8.10 usb status register 0 r0seq ?endpoint 0 receive sequence bit this read-only bit indicates the type of data packet last received for endpoint 0 (data0 or data1). 1 = data1 token received in last endpoint 0 receive 0 = data0 token received in last endpoint 0 receive setup ?setup token detect bit this read-only bit indicates that a valid setup token has been received. 1 = last token received for endpoint 0 was a setup token 0 = last token received for endpoint 0 was not a setup token rp0siz3?p0siz0 ?endpoint 0 receive data packet size these read-only bits store the number of data bytes received for the last out or setup transaction for endpoint 0. address: $003d bit 7 654321 bit 0 read: r0seq setup 0 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: reset: unaffected by reset = unimplemented figure 9-24. usb status register 0 (usr0)
universal serial bus module (usb) i/o register description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 129 9.8.11 usb status register 1 txack ?ack token transmit bit this read-only bit indicates that an ack token has been transmitted. this bit is updated at the end of the data transmission. 1 = last token transmitted for endpoint 0 was an ack token 0 = last token transmitted for endpoint 0 was not an ack token txnak ?nak token transmit bit this read-only bit indicates that a txnak token has been transmitted. this bit is updated at the end of the data transmission. 1 = last token transmitted for endpoint 0 was a nak token 0 = last token transmitted for endpoint 0 was not a nak token txstl ?stall token transmit bit this read-only bit indicates that a stall token has been transmitted. this bit is updated at the end of the data transmission. 1 = last token transmitted for endpoint 0 was a stall token 0 = last token transmitted for endpoint 0 was not a stall token address: $003e bit 7 654321 bit 0 read: 0 txack txnak txstl 0000 write: reset: 00000000 = unimplemented u = unaffected by reset figure 9-25. usb status register 2 (usr1)
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 130 universal serial bus module (usb) motorola 9.8.12 usb endpoint 0 data registers ue0rx7?e0rx0 ?endpoint 0 receive data buffer these read-only bits are serially loaded with out token or setup token data directed at endpoint 0. the data is received over the usb? d+ and d?pins. ue0tx7?e0tx0 ?endpoint 0 transmit data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 0. address: $0020 ue0d0 bit 7 654321 bit 0 read: ue0r07 ue0r06 ue0r05 ue0r04 ue0r03 ue0r02 ue0r01 ue0r00 write: ue0t07 ue0t06 ue0t05 ue0t04 ue0t03 ue0t02 ue0t01 ue0t00 reset: unaffected by reset address: $0027 ue0d7 read: ue0r77 ue0r76 ue0r75 ue0r74 ue0r73 ue0r72 ue0r71 ue0r70 write: ue0t77 ue0t76 ue0t75 ue0t74 ue0t73 ue0t72 ue0t71 ue0t70 reset: unaffected by reset figure 9-26. usb endpoint 0 data register (ue0d0?e0d7)
universal serial bus module (usb) i/o register description MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 131 9.8.13 usb endpoint 1 data registers ue1tx7?e1tx0 ?endpoint 1 transmit or receive data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 1. address: $0028 ue1d0 bit 7 654321 bit 0 read: write: ue1t07 ue1t06 ue1t05 ue1t04 ue1t03 ue1t02 ue1t01 ue1t00 reset: unaffected by reset address: $002f ue1d7 read: write: ue1t77 ue1t76 ue1t75 ue1t74 ue1t73 ue1t72 ue1t71 ue1t70 reset: unaffected by reset = unimplemented figure 9-27. usb endpoint 1 data register (ue1d0?e1d7)
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 132 universal serial bus module (usb) motorola 9.8.14 usb endpoint 2 data registers ue2tx7?e2tx0 ?endpoint 2 transmit data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 2. address: $0030 ue2d0 bit 7 654321 bit 0 read: write: ue2t07 ue2t06 ue2t05 ue2t04 ue2t03 ue2t02 ue2t01 ue2t00 reset: unaffected by reset address: $0037 ue2d7 read: write: ue2t77 ue2t76 ue2t75 ue2t74 ue2t73 ue2t72 ue2t71 ue2t70 reset: unaffected by reset figure 9-28. usb endpoint 2 data register (ue2d0?e2d7)
universal serial bus module (usb) usb interrupts MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 133 9.9 usb interrupts the usb module is capable of generating interrupts and causing the cpu to execute the usb interrupt service routine. there are three types of usb interrupts: end-of-transaction interrupts signify either a completed transaction receive or transmit transaction. resume interrupts signify that the usb bus is reactivated after having been suspended. end-of-packet interrupts signify that a low-speed end-of-packet signal was detected. all usb interrupts share the same interrupt vector. firmware is responsible for determining which interrupt is active. 9.9.1 usb end-of-transaction interrupt there are four possible end-of-transaction interrupts: endpoint 0 receive endpoint 0, 1 or 2 transmit end-of-transaction interrupts occur as detailed in the following sections.
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 134 universal serial bus module (usb) motorola 9.9.1.1 receive control endpoint 0 for a control out transaction directed at endpoint 0, the usb module will generate an interrupt by setting the rxd0f flag in the uir0 register. the conditions necessary for the interrupt to occur are shown in the flowchart in figure 9-29 . figure 9-29. out token data flow for receive endpoint 0 valid out token received for endpoint 0 error free data packet? no response from usb function set rxd0f to 1 (rxd0ie = 1) no interrupt accept data no response from usb function timeout n set/clear r0seq bit valid data token received for endpoint 0? usb module enabled? (usben = 1) endpoint 0 receive not stalled? (ostall0 = 0) endpoint 0 receive ready to receive? (rx0e = 1) and (rxd0f = 0) receive control endpoint interrupt enabled? valid transaction interrupt generated send stall handshake send nak handshake no response from usb function ignore transaction y y y y y y n n n n n y
universal serial bus module (usb) usb interrupts MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 135 setup transactions cannot be stalled by the usb function. a setup received by a control endpoint will clear the istall0 and ostall0 bits. the conditions for receiving a setup interrupt are shown in figure 9-30 . figure 9-30. setup token data flow for receive endpoint 0 error free data packet? no response from usb function set rxd0f to 1 (rxd0ie = 1) no interrupt accept data n set/clear r0seq bit valid setup token received for endpoint 0? usb module enabled? (usben = 1) endpoint 0 receive ready to receive? (rx0e = 1) and (rxd0f = 0) receive control endpoint interrupt enabled? valid transaction interrupt generated no response from usb function clear istall0 and ostall bits no response from usb function ignore transaction y y y y y y n n n n (istall0 = 0) and (ostall = 0)? set setup bit to 1
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 136 universal serial bus module (usb) motorola 9.9.1.2 transmit control endpoint 0 for a control in transaction directed at endpoint 0, the usb module will generate an interrupt by setting the txd0f flag in the uir1 register. the conditions necessary for the interrupt to occur are shown in the flowchart in figure 9-31 . figure 9-31. in token data flow for transmit endpoint 0 valid in token received for endpoint 0 send stall handshake set txd0f to 1 (txd0ie = 1) no interrupt send data n data pid set by t0seq usb module enabled? (usben = 1) transmit endpoint not stalled by firmware (istall0 = 0)? transmit endpoint ready to transfer? (tx0e = 1) and (txd0f = 0) transmit endpoint interrupt enabled? valid transaction interrupt generated send nak handshake y y y y y n n n n y no response from usb function ack received and no timeout condition occurs? no response from usb function
universal serial bus module (usb) usb interrupts MC68HC08JB1 ? rev. 1.0 technical data motorola universal serial bus module (usb) 137 9.9.1.3 transmit endpoint 1 for an in transaction directed at endpoint 1, the usb module will generate an interrupt by setting the txd1f in the uir1 register. the conditions necessary for the interrupt to occur are shown in figure 9-32 . figure 9-32. in token data flow for transmit endpoint 1 valid in token received for endpoint 1 send stall handshake set txd1f to 1 (txd1ie = 1) no interrupt send data n data pid set by t1seq usb module enabled? (usben = 1) transmit endpoint not stalled by firmware (stall1 = 1)? transmit endpoint ready to transfer? (tx1e = 1) and (txd1f = 0) and (ue1tr = 0) transmit endpoint enabled? (enable = 1) transmit endpoint interrupt enabled? valid transaction interrupt generated send nak handshake no response from usb function y y y y y y n n n n n y no response from usb function ack received and no timeout condition occurs? no response from usb function
universal serial bus module (usb) technical data MC68HC08JB1 ? rev. 1.0 138 universal serial bus module (usb) motorola 9.9.1.4 transmit endpoint 2 for an in transaction directed at endpoint 2, the usb module will generate an interrupt by setting the txd2f in the uir1 register. 9.9.2 resume interrupt the usb module will generate a cpu interrupt if low-speed bus activity is detected after entering the suspend state. a transition of the usb data lines to the non-idle state (k state) while in the suspend mode will set the resumf flag in the uir1 register. there is no interrupt enable bit for this interrupt source and an interrupt will be executed if the i bit in the ccr is cleared. a resume interrupt can only occur while the mcu is in the suspend mode. 9.9.3 end-of-packet interrupt the usb module can generate a usb interrupt upon detection of an end-of-packet signal for low-speed devices. upon detection of an end-of-packet signal, the usb module sets the eopf bit and will generate a cpu interrupt if the eopie bit in the uir0 register is set.
MC68HC08JB1 ? rev. 1.0 technical data motorola timer interface module (tim) 139 technical data ?MC68HC08JB1 section 10. timer interface module (tim) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 144 10.5.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . 144 10.5.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . 145 10.5.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . 146 10.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 147 10.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.8.1 tim clock pin (pte0/tclk) . . . . . . . . . . . . . . . . . . . . . . . 151 10.8.2 tim channel i/o pins (pte1/tch0:pte2/tch1) . . . . . . . 151 10.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.9.1 tim status and control register . . . . . . . . . . . . . . . . . . . . 152 10.9.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 10.9.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . 155 10.9.4 tim channel status and control registers . . . . . . . . . . . . 156 10.9.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
timer interface module (tim) technical data MC68HC08JB1 ? rev. 1.0 140 timer interface module (tim) motorola 10.2 introduction this section describes the timer interface module (tim2, version b). the tim is a 2-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 10-1 is a block diagram of the tim. note: tch1 and tclk pins are not available on this timer. 10.3 features features of the tim include: input capture/output compare channel rising-edge, falling-edge, or any-edge input capture trigger set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input 7-frequency internal bus clock prescaler selection free-running or modulo up-count operation toggle any channel pin on overflow tim counter stop and reset bits modular architecture expandable to eight channels 10.4 pin name conventions the tim share three i/o pins with three port e i/o pins. the full name of the tim i/o pin is listed in table 10-1 . the generic pin name appear in the text that follows. table 10-1. tim pin name conventions tim generic pin names: tclk tch0 tch1 full tim pin names: not available pte1/tch0 not available
timer interface module (tim) functional description MC68HC08JB1 ? rev. 1.0 technical data motorola timer interface module (tim) 141 10.5 functional description figure 10-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodh:tmodl, control the modulo value of the tim counter. software can read the tim counter value at any time without affecting the counting sequence. the two tim channels are programmable independently as input capture or output compare channels. figure 10-1. tim block diagram prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus ms1a internal bus clock tch1 tch0 interrupt logic port logic interrupt logic interrupt logic port logic tclk (not available) (not available)
timer interface module (tim) technical data MC68HC08JB1 ? rev. 1.0 142 timer interface module (tim) motorola addr. register name bit 7 654321 bit 0 $000a tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 $000c tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: 00000000 $000d tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: 00000000 $000e tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: 11111111 $000f tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: 11111111 $0010 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 $0011 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0012 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0013 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 = unimplemented figure 10-2. tim i/o register summary
timer interface module (tim) functional description MC68HC08JB1 ? rev. 1.0 technical data motorola timer interface module (tim) 143 10.5.1 tim counter prescaler the tim clock source can be one of the seven prescaler outputs or the tim clock pin, pte0/tclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register (tsc) select the tim clock source. 10.5.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tim latches the contents of the tim counter into the tim channel registers, tchxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 10.5.3 output compare with the output compare function, the tim can generate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. $0014 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0015 tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset = unimplemented figure 10-2. tim i/o register summary
timer interface module (tim) technical data MC68HC08JB1 ? rev. 1.0 144 timer interface module (tim) motorola 10.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 10.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable channel x tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 10.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the pte1/tch0 pin. the tim channel registers of the linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output compare value in the tim
timer interface module (tim) functional description MC68HC08JB1 ? rev. 1.0 technical data motorola timer interface module (tim) 145 channel 0 registers initially controls the output on the pte1/tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte2/tch1, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. 10.5.4 pulse width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between overflows is the period of the pwm signal. as figure 10-3 shows, the output compare value in the tim channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on output compare if the state of the pwm pulse is logic 1. program the tim to set the pin if the state of the pwm pulse is logic 0.
timer interface module (tim) technical data MC68HC08JB1 ? rev. 1.0 146 timer interface module (tim) motorola figure 10-3. pwm period and pulse width the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is 000 (see 10.9.1 tim status and control register ). the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. 10.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 10.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow interrupt routine to ptex/tchxa period pulse width overflow overflow overflow output compare output compare output compare
timer interface module (tim) functional description MC68HC08JB1 ? rev. 1.0 technical data motorola timer interface module (tim) 147 write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 10.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte1/tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the pte1/tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and
timer interface module (tim) technical data MC68HC08JB1 ? rev. 1.0 148 timer interface module (tim) motorola control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte2/tch1, is available as a general-purpose i/o pin. note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered pwm signals. 10.5.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use this initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb:msxa. (see table 10-3.) b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 10-3 .) note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value.
timer interface module (tim) interrupts MC68HC08JB1 ? rev. 1.0 technical data motorola timer interface module (tim) 149 5. in the tim status control register (tsc), clear the tim stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h:tch0l) initially control the buffered pwm output. tim status control register 0 (tscr0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and clearing the tovx bit generates a 100% duty cycle output. (see 10.9.4 tim channel status and control registers .) 10.6 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ?the tof bit is set when the tim counter value rolls over to $0000 after matching the value in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. tim channel flags (ch1f:ch0f) ?the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie = 1. chxf and chxie are in the tim channel x status and control register. 10.7 wait mode the wait instruction puts the mcu in low-power-consumption standby mode.
timer interface module (tim) technical data MC68HC08JB1 ? rev. 1.0 150 timer interface module (tim) motorola the tim remains active after the execution of a wait instruction. in wait mode the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim before executing the wait instruction. 10.8 i/o signals port e shares three of its pins with the tim. pte0/tclk is an external clock input to the tim prescaler. the two tim channel i/o pins are pte1/tch0 and pte2/tch1.
timer interface module (tim) i/o registers MC68HC08JB1 ? rev. 1.0 technical data motorola timer interface module (tim) 151 10.8.1 tim clock pin (pte0/tclk) pte0/tclk is an external clock input that can be the clock source for the tim counter instead of the prescaled internal bus clock. select the pte0/tclk input by writing logic 1s to the three prescaler select bits, ps[2:0]. (see 10.9.1 tim status and control register .) the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is: bus frequency ? 2 pte0/tclk is available as a general-purpose i/o pin when not used as the tim clock input. when the pte0/tclk pin is the tim clock input, it is an input regardless of the state of the ddre0 bit in data direction register e. 10.8.2 tim channel i/o pins (pte1/tch0:pte2/tch1) each channel i/o pin is programmable independently as an input capture pin or an output compare pin. pte1/tch0 can be configured as buffered output compare or buffered pwm pins. 10.9 i/o registers the following i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim control registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and control registers (tsc0 and tsc1) tim channel registers (tch0h:tch0l and tch1h:tch1l) 1 bus frequency ------------------------------------- t su +
timer interface module (tim) technical data MC68HC08JB1 ? rev. 1.0 152 timer interface module (tim) motorola 10.9.1 tim status and control register the tim status and control register: enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ?tim overflow flag bit this read/write flag is set when the tim counter resets to $0000 after reaching the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a logic 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = tim counter has reached modulo value. 0 = tim counter has not reached modulo value. toie ?tim overflow interrupt enable bit this read/write bit enables tim overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tim overflow interrupts enabled. 0 = tim overflow interrupts disabled. address: $000a bit 7 654321 bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 = unimplemented figure 10-4. tim status and control register (tsc)
timer interface module (tim) i/o registers MC68HC08JB1 ? rev. 1.0 technical data motorola timer interface module (tim) 153 tstop ?tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. trst ?tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim counter is reset and always reads as logic 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] ?prescaler select bits these read/write bits select either the pte0/tclk pin or one of the seven prescaler outputs as the input to the tim counter as table 10-2 shows. reset clears the ps[2:0] bits. table 10-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock ? 1 0 0 1 internal bus clock ? 2 0 1 0 internal bus clock ? 4 0 1 1 internal bus clock ? 8 1 0 0 internal bus clock ? 16 1 0 1 internal bus clock ? 32 1 1 0 internal bus clock ? 64 1 1 1 pte0/tclk
timer interface module (tim) technical data MC68HC08JB1 ? rev. 1.0 154 timer interface module (tim) motorola 10.9.2 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. tcnth address: $000c bit 7 654321 bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 00000000 tcntl address: $000d bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 00000000 = unimplemented figure 10-5. tim counter registers (tcnth:tcntl)
timer interface module (tim) i/o registers MC68HC08JB1 ? rev. 1.0 technical data motorola timer interface module (tim) 155 10.9.3 tim counter modulo registers the read/write tim modulo registers contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note: reset the tim counter before writing to the tim counter modulo registers. tmodh address: $000e bit 7 654321 bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 11111111 tmodl address: $000f bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 11111111 figure 10-6. tim counter modulo registers (tmodh:tmodl)
timer interface module (tim) technical data MC68HC08JB1 ? rev. 1.0 156 timer interface module (tim) motorola 10.9.4 tim channel status and control registers each of the tim channel status and control registers does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tim overflow selects 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation tsc0 address: $0010 bit 7 654321 bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 tsc1 address: $0013 bit 7 654321 bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 = unimplemented figure 10-7. tim channel status and control registers (tsc0:tsc1)
timer interface module (tim) i/o registers MC68HC08JB1 ? rev. 1.0 technical data motorola timer interface module (tim) 157 chxf ?channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. when tim cpu interrupt requests are enabled (chxie = 1), clear chxf by reading the tim channel x status and control register with chxf set and then writing a logic 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ?channel x interrupt enable bit this read/write bit enables tim cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ?mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim channel 0 status and control register. setting ms0b disables the channel 1 status and control register and reverts tch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ?mode select bit a when elsxb:a 1 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 10-3 . 1 = unbuffered output compare/pwm operation 0 = input capture operation
timer interface module (tim) technical data MC68HC08JB1 ? rev. 1.0 158 timer interface module (tim) motorola when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin. (see table 10-3.). reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). elsxb and elsxa ?edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port e, and pin ptex/tchx is available as a general-purpose i/o pin. table 10-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. table 10-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x000 output preset pin under port control; initial output level high x100 pin under port control; initial output level low 0001 input capture capture on rising edge only 0010 capture on falling edge only 0011 capture on rising or falling edge 0101 output compare or pwm toggle output on compare 0110 clear output on compare 0111 set output on compare 1 x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare
timer interface module (tim) i/o registers MC68HC08JB1 ? rev. 1.0 technical data motorola timer interface module (tim) 159 note: before enabling a tim channel register for input capture operation, make sure that the ptex/tchx pin is stable for at least two bus clocks. tovx ?toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not toggle on tim counter overflow. note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ?channel x maximum duty cycle bit when the tovx bit is at logic 0, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 10-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 10-8. chxmax latency output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare
timer interface module (tim) technical data MC68HC08JB1 ? rev. 1.0 160 timer interface module (tim) motorola 10.9.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading the high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 1 0:0), writing to the high byte of the tim channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. tch0h address: $0011 bit 7 654321 bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset tch0l address: $0012 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset tch1h address: $0014 bit 7 654321 bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset tch1l address: $0015 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 10-9. tim channel registers (tch0h/l:tch1h/l)
MC68HC08JB1 ? rev. 1.0 technical data motorola input/output ports (i/o) 161 technical data ?MC68HC08JB1 section 11. input/output ports (i/o) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 11.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 11.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 164 11.4 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11.4.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11.4.2 data direction register c. . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.5 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.5.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.5.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.6 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.6.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.6.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.7 port options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.7.1 port option control register . . . . . . . . . . . . . . . . . . . . . . . 175 11.2 introduction thirteen bidirectional input-output (i/o) pins form four parallel ports. all i/o pins are programmable as inputs or outputs.
input/output ports (i/o) technical data MC68HC08JB1 ? rev. 1.0 162 input/output ports (i/o) motorola note: connect any unused i/o pins to an appropriate logic level, either v reg or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. addr. register name bit 7 654321 bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 0000000 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: 000000 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0* 0000000 * ddra7 bit is reset by por or lvi reset only. $0006 data direction register c (ddrc) read: 0000000 ddrc0 write: reset: 00000000 $0007 data direction register d (ddrd) read: 000000 ddrd1 ddrd0 write: reset: 00000000 $0008 port e data register (pte) read: 0 0 0 pte4 pte3 0 pte1 0 write: reset: unaffected by reset $0009 data direction register e (ddre) read: 0 0 0 ddre4 ddre3 0 ddre1 0 write: reset: 00000000 $001d port option control register (pocr) read: pte20p 0 ptdildd pte4p pte3p pcp 0 pa p write: reset: 00000000 = unimplemented figure 11-1. i/o port register summary
input/output ports (i/o) port a MC68HC08JB1 ? rev. 1.0 technical data motorola input/output ports (i/o) 163 11.3 port a port a is an 8-bit general-purpose bidirectional i/o port with software configurable pullups, and it shares its pins with the keyboard interrupt module (kbi). 11.3.1 port a data register the port a data register contains a data latch for each of the eight port a pins. pta[7:0] ?port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. the port a pullup control bit, pap, enables pullups on port a pins if the respective pin is configured as an input. (see 11.7 port options .) kba7 ?ba0 ?keyboard interrupts the keyboard interrupt enable bits, kba7 ?ba0 , in the keyboard interrupt enable register (kbier), enable the port a pins as external interrupt pins. (see section 13. keyboard interrupt module (kbi) .) address: $0000 bit 7 654321 bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternative function: kba7 kba6 kba5 kba4 kba3 kba2 kba1 kba0 additional function: optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup 5.5 v rating figure 11-2. port a data register (pta)
input/output ports (i/o) technical data MC68HC08JB1 ? rev. 1.0 164 input/output ports (i/o) motorola 11.3.2 data direction register a data direction register a determines whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables the output buffer for the corresponding port a pin; a logic 0 disables the output buffer. ddra[7:0] ?data direction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 11-4 shows the port a i/o logic. figure 11-4. port a i/o circuit address: $0004 bit 7 654321 bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0* 0000000 * ddra7 bit is reset by por or lvi reset only. figure 11-3. data direction register a (ddra) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus
input/output ports (i/o) port a MC68HC08JB1 ? rev. 1.0 technical data motorola input/output ports (i/o) 165 when bit ddrax is a logic 1, reading address $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-1 summarizes the operation of the port a pins. table 11-1. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0 x (1) 1. x = don? care input, hi-z (2) 2. hi-z = high impedance ddra[7:0] pin pta[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddra[7:0] pta[7:0] pta[7:0]
input/output ports (i/o) technical data MC68HC08JB1 ? rev. 1.0 166 input/output ports (i/o) motorola 11.4 port c port c is an 1-bit general-purpose bidirectional i/o port with software configurable pullups and current drive options. 11.4.1 port c data register the port c data register contains a data latch for the ptc0 pin. ptc0 ?port c data bit-0 this read/write bit is software-programmable. data direction is under the control of the ddrc0 bit in data direction register c. reset has no effect on ptc0 data. the port c pullup enable bit, pcp, in the port option control register (pocr) enables a pullup on ptc0 if the pin is configured as an input. (see 11.7 port options .) address: $0002 bit 7 654321 bit 0 read: 0000000 ptc0 write: reset: unaffected by reset additional function: optional pullup figure 11-5. port c data register (ptc)
input/output ports (i/o) port c MC68HC08JB1 ? rev. 1.0 technical data motorola input/output ports (i/o) 167 11.4.2 data direction register c data direction register c determines whether ptc0 pin is an input or an output. writing a logic 1 to ddrc0 bit enables the output buffer for the ptc0 pin; a logic 0 disables the output buffer. ddrc 0 ?data direction register c bit-0 this read/write bit control ptc0 data direction. reset clears ddrc0, configuring ptc0 pin as an input. 1 = ptc0 pin configured as output 0 = ptc0 pin configured as input note: avoid glitches on ptc0 pin by writing to the port c data register before changing ddrc0 bit from 0 to 1. figure 11-7 shows the port c i/o logic. figure 11-7. port c i/o circuit address: $0006 bit 7 654321 bit 0 read: 0000000 ddrc0 write: reset: 00000000 figure 11-6. data direction register c (ddrc) read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptc0 ddrc0 ptc0 internal data bus
input/output ports (i/o) technical data MC68HC08JB1 ? rev. 1.0 168 input/output ports (i/o) motorola when bit ddrc0 is a logic 1, reading address $0002 reads the ptc0 data latch. when bit ddrc0 is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-2 summarizes the operation of the ptc0 pin. 11.5 port d port d is an 1-bit general-purpose bidirectional i/o port. ptd1 and ptd0 internal pads are bonded together to form ptd0/1 pin. this pin is open- drain when configured as output, and can interface with 5v logic. 11.5.1 port d data register the port d data register contains a data latch for the ptd0/1 pin. table 11-2. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 ptc0 input, hi-z (1) 1. hi-z = high impedance ddrc0 pin ptc0 (2) 2. writing affects data register, but does not affect input. 1 ptc0 output ddrc0 ptc0 ptc0 address: $0003 bit 7 654321 bit 0 read: 000000 ptd1 ptd0 write: reset: unaffected by reset additional function: 25 ma sink 25 ma sink figure 11-8. port d data register (ptd)
input/output ports (i/o) port d MC68HC08JB1 ? rev. 1.0 technical data motorola input/output ports (i/o) 169 ptd[1:0] ?port d data bit-1 and bit-0 these two read/write bits are software programmable. data direction of ptd0/1 pin is under control of these two data bits. reset has no effect on port d data. configure this register so that ptd1 = ptd0. the infrared led drive bit, ptdildd, in the port option control register (pocr) controls the drive options for ptd[1:0]. (see 11.7 port options .) note: ptd1 and ptd0 internal pads are bonded together to ptd0/1 pin forming a 50ma high current drain pin. when both ptd1 and ptd0 are configured as output, the values of ptd0 and ptd1 should be written the same. 11.5.2 data direction register d data direction register d determines whether ptd0/1 pin is an input or an output. writing a logic 1 to ddrd[1:0] bits enable the output buffer for the ptd0/1 pin; a logic 0 disables the output buffer. ddrd[1:0] ?data direction register d bit-1 and bit-0 these two read/write bits control ptd0/1 pin data direction. reset clears ddrd[1:0], configuring ptd0/1 pin as an input. configure this register so that ddrd1 = ddrd0. 1 = ptd0/1 pin configured as output 0 = ptd0/1 pin configured as input note: avoid glitches on ptd0/1 pin by writing to ptd[1:0] before changing ddrd[1:0] bits from 0 to 1. address: $0007 bit 7 654321 bit 0 read: 000000 ddrd1 ddrd0 write: reset: 00000000 figure 11-9. data direction register d (ddrd)
input/output ports (i/o) technical data MC68HC08JB1 ? rev. 1.0 170 input/output ports (i/o) motorola figure 11-10 shows the port d i/o circuit logic. figure 11-10. port d i/o circuit when bit ddrd[1:0] is a logic 1, reading address $0003 reads the ptd0/1 data latch. when bit ddrd[1:0] is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-3 summarizes the operation of the port d pins. table 11-3. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0 ptd[1:0] input, hi-z (1) 1. hi-z = high impedance ddrd[1:0] pin ptd[1:0] (2) 2. writing affects data register, but does not affect input. 1 ptd[1:0] output ddrd[1:0] ptd0/1 ptd[1:0] read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptd0/1 ddrd1/ddrd0 ptd1/ptd0 internal data bus
input/output ports (i/o) port e MC68HC08JB1 ? rev. 1.0 technical data motorola input/output ports (i/o) 171 11.6 port e port e is a 3-bit special function port that shares one of its pins with the timer interface module (tim) and two of its pins with the usb data pins d+ and d? 11.6.1 port e data register the port e data register contains a data latch for each of the three port e pins. pte4, pte3, pte1?port e data bits pte4, pte3, and pte1 are read/write, software-programmable bits. data direction of each port e pin is under the control of the corresponding bit in data direction register e. the pte4 and pte3 pullup enable bits, pte4p and pte3p, in the port option control register (pocr) enable 5k w pullups on pte4 and pte3 if the respective pin is configured as an input and the usb module is disabled. (see 11.7 port options .) the pte1 pullup enable bit, pte20p, in the port option control register (pocr) enables pullup on pte1, regardless of the pin is configured as an input or an output. (see 11.7 port options .) address: $0008 bit 7 654321 bit 0 read: 0 0 0 pte4 pte3 0 pte1 0 write: reset: unaffected by reset alternative function: d d+ tch0 additional function: optional pullup optional pullup optional pullup additional function: external interrupt = unimplemented figure 11-11. port e data register (pte)
input/output ports (i/o) technical data MC68HC08JB1 ? rev. 1.0 172 input/output ports (i/o) motorola pte4 pin functions as an external interrupt when pte4ie=1 in the irq option control register (iocr) and usben=0 in the usb address register (usb disabled). (see 12.9 irq option control register .) d?and d+ ?usb data pins d?and d+ are the differential data lines used by the usb module. (see section 9. universal serial bus module (usb) .) the usb module enable bit, usben, in the usb address register (uaddr) controls the pin options for pte4/d?and pte3/d+. when the usb module is enabled, pte4/d?and pte3/d+ function as usb data pins d?and d+. when the usb module is disabled, pte4/d? and pte3/d+ function as 10ma open drain high current pins for ps/2 clock and data use. the pullup enable bit, pullen, in the usb control register 3 (ucr3) enables a 1.5k w pullup on d?pin when the usb module is enabled. (see 9.8.8 usb control register 3 .) note: pte4/d?pin has two programmable pullup resistors. one is used for pte4 when the usb module is disabled and another is used for d? when the usb module is enabled. tch0 ?timer channel 0 i/o bits the pte1/tch0 pin is the tim input capture/output compare pin. the edge/level select bits, els0b and els0a, determine whether the pte1/tch0 pin is timer channel i/o pin or general-purpose i/o pin. (see section 10. timer interface module (tim) .) note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the tim. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins.
input/output ports (i/o) port e MC68HC08JB1 ? rev. 1.0 technical data motorola input/output ports (i/o) 173 11.6.2 data direction register e data direction register e determines whether each port e pin is an input or an output. writing a logic 1 to a ddre bit enables the output buffer for the corresponding port e pin; a logic 0 disables the output buffer. ddre4, ddre3, ddre1 ?data direction register e bits these read/write bits control port e data direction. reset clears ddre4, ddre3, and ddre1, configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pins by writing to the port e data register before changing data direction register e bits from 0 to 1. figure 11-13 shows the port e i/o circuit logic. figure 11-13. port e i/o circuit address: $0009 bit 7 654321 bit 0 read: 0 0 0 ddre4 ddre3 0 ddre1 0 write: reset: 00000000 = unimplemented figure 11-12. data direction register e (ddre) read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus
input/output ports (i/o) technical data MC68HC08JB1 ? rev. 1.0 174 input/output ports (i/o) motorola when bit ddrex is a logic 1, reading address $0008 reads the ptex data latch. when bit ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-2 summarizes the operation of the port e pins. 11.7 port options all pins of port a, port c, and port e have programmable pullup resistors. port d has led drive capability. port pins pte4 and pte3 have 10ma high current drive capability. table 11-4. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0 pte4 pte3 pte1 input, hi-z (1) 1. hi-z = high impedance ddre4 ddre3 ddre1 pin pte4 (2) pte3 pte1 2. writing affects data register, but does not affect input. 1 pte4 pte3 pte1 output ddre4 ddre3 ddre1 pte4 pte3 pte1 pte4 pte3 pte1
input/output ports (i/o) port options MC68HC08JB1 ? rev. 1.0 technical data motorola input/output ports (i/o) 175 11.7.1 port option control register the port option control register controls the pullup options for port a, port b, port c, and port e pins. it also controls the drive configuration on port d. pte20p ?pte1 pin pullup enable this read/write bit controls the pullup option for the pte1 pins. 1 = configure pte1 to have internal pullups. 0 = disconnect pte1 internal pullups. ptdildd ?infrared led drive control this read/write bit controls the output current capability of ptd[1:0]. when set, the ptd[1:0] have high current ability so that an infrared led can be connected directly between the port pin and v dd . 1 = when respective port is configured as an output, make ptd[1:0] become 25 ma open drain sink port pins. 0 = configure ptd[1:0] to become standard open drain i/o port pins. pte4p ?pin pte4 pullup enable this read/write bit controls the pullup option for the pte4 pin when the usb module is disabled. 1 = configure pte4 to have internal pullup. 0 = disconnect pte4 internal pullup. note: when the usb module is enabled, the pullup controlled by pte4p is disconnected; pte4/d?pin functions as d?which has a 1.5k w programmable pull-up resistor. (see 9.8.8 usb control register 3 .) address: $001d bit 7 654321 bit 0 read: pte20p 0 ptdildd pte4p pte3p pcp 0 pa p write: reset: 00000000 figure 11-14. port option control register (pocr)
input/output ports (i/o) technical data MC68HC08JB1 ? rev. 1.0 176 input/output ports (i/o) motorola pte3p ?pin pte3 pullup enable this read/write bit controls the pullup option for the pte3 pin when the usb module is disabled. 1 = configure pte3 to have internal pullup. 0 = disconnect pte3 internal pullup. pcp ?port c pullup enable this read/write bit controls the pullup option for the eight bits of port c if its respective port pin is configured as an input. 1 = configure port c to have internal pullups. 0 = disconnect port c internal pullups. pap ?port a pullup enable this read/write bit controls the pullup option for the eight bits of port a if its respective port pin is configured as an input. 1 = configure port a to have internal pullups. 0 = disconnect port a internal pullups.
MC68HC08JB1 ? rev. 1.0 technical data motorola external interrupt (irq) 177 technical data ?MC68HC08JB1 section 12. external interrupt (irq) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 12.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 12.6 pte4/d?pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 12.7 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 181 12.8 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 182 12.9 irq option control register. . . . . . . . . . . . . . . . . . . . . . . . . . 183 12.2 introduction the irq module provides two external interrupt inputs: one dedicated irq pin and one shared port pin, pte4/d? 12.3 features features of the irq module include: two external interrupt pins, irq (5v) and pte4/d?(5v) irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge low leakage irq pin for external rc wake up input selectable internal pullup resistor
external interrupt (irq) technical data MC68HC08JB1 ? rev. 1.0 178 external interrupt (irq) motorola 12.4 functional description a logic 0 applied to the external interrupt pin can latch a cpu interrupt request. figure 12-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq1 latch. an interrupt latch remains set until one of the following actions occurs: vector fetch ?a vector fetch automatically generates an interrupt acknowledge signal that clears the irq1 latch. software clear ?software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (iscr). writing a logic 1 to the ack1 bit clears the irq1 latch. reset ?a reset automatically clears the interrupt latch. the external interrupt pin is falling-edge-triggered and is software- configurable to be either falling-edge or low-level-triggered. the mode1 bit in the iscr controls the triggering sensitivity of the irq pin. when the interrupt pin is edge-triggered only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both falling-edge and low-level-triggered, the cpu interrupt request remains set until both of the following occur: vector fetch or software clear return of the interrupt pin to logic one the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode1 control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask1 bit in the iscr mask all external interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the imask1 bit is clear. note: the interrupt mask (i) in the condition code register (ccr) masks all interrupt requests, including external interrupt requests. (see 8.6 exception control .)
external interrupt (irq) functional description MC68HC08JB1 ? rev. 1.0 technical data motorola external interrupt (irq) 179 figure 12-1. irq module block diagram addr. register name bit 7 654321 bit 0 $001c irq option control register (iocr) read: 00000 pte4if pte4ie irqpd write: reset: 00000000 $001e irq status/control register (iscr) read: 0000 irqf1 0 imask1 mode1 write: ack1 reset: 00000000 = unimplemented figure 12-2. irq i/o register summary ack1 imask1 dq ck clr irq1 high interrupt to mode select logic irq ff request v reg mode1 voltage detect synchro- nizer irqf1 to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd i nternal pullup device dq ck clr v reg pte4if pte4ie pte4 irq irqpd read iocr to pte4 pullup enable circuitry
external interrupt (irq) technical data MC68HC08JB1 ? rev. 1.0 180 external interrupt (irq) motorola 12.5 irq pin the irq pin has a low leakage for input voltages ranging from 0v to v dd ; suitable for applications using rc discharge circuitry to wake up the mcu. a logic 0 on the irq pin can latch an interrupt request into the irq1 latch. a vector fetch, software clear, or reset clears the irq1 latch. if the mode1 bit is set, the irq pin is both falling-edge-sensitive and low-level-sensitive. with mode1 set, both of the following actions must occur to clear irq1: vector fetch or software clear ?a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a logic 1 to the ack1 bit in the interrupt status and control register (iscr). the ack1 bit is useful in applications that poll the irq pin and require software to clear the irq1 latch. writing to the ack1 bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ack1 does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack1 bit latches another interrupt request. if the irq1 mask bit, imask1, is clear, the cpu loads the program counter with the vector address at locations $fff8 and $fff9. return of the irq pin to logic one ?as long as the irq pin is at logic zero, irq1 remains active. the vector fetch or software clear and the return of the irq pin to logic one may occur in any order. the interrupt request remains pending as long as the irq pin is at logic zero. a reset will clear the latch and the mode1 control bit, thereby clearing the interrupt even if the pin stays low. if the mode1 bit is clear, the irq pin is falling-edge-sensitive only. with mode1 clear, a vector fetch or software clear immediately clears the irq1 latch.
external interrupt (irq) pte4/d?pin MC68HC08JB1 ? rev. 1.0 technical data motorola external interrupt (irq) 181 the irqf1 bit in the iscr register can be used to check for pending interrupts. the irqf1 bit is not affected by the imask1 bit, which makes it useful in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq pin. note: when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. note: an internal pullup resistor to v dd is connected to irq pin; this can be disabled by setting the irqpd bit in the irq option control register ($001c). 12.6 pte4/d?pin the pte4 pin is configured as an interrupt input to trigger the irq1 interrupt when the following conditions are satisfied: the usb module is disabled (usben = 0) pte4 pin configured for external interrupt input (pte4ie = 1) setting pte4ie configures the pte4 pin to an input pin with an internal pullup device. the pte4 interrupt is "ored" with the irq input to trigger the irq1 interrupt (see figure 12-1 . irq module block diagram ). therefore, the irq status and control register affects both the irq pin and the pte pin. an interrupt on pte4 also sets the pte4 interrupt flag, pte4if, in the irq option control register (iocr). 12.7 irq module during break interrupts the system integration module (sim) controls whether the irq1 latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear the latches during the break state. (see section 8. system integration module (sim) .) to allow software to clear the irq1 latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state.
external interrupt (irq) technical data MC68HC08JB1 ? rev. 1.0 182 external interrupt (irq) motorola to protect the latches during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the ack1 bit in the irq status and control register during the break state has no effect on the irq latch. 12.8 irq status and control register the irq status and control register (iscr) controls and monitors operation of the irq module. the iscr has the following functions: shows the state of the irq1 flag clears the irq1 latch masks irq1 interrupt request controls triggering sensitivity of the irq pin. irqf1 ?irq1 flag this read-only status bit is high when the irq1 interrupt is pending. 1 = irq1 interrupt pending 0 = irq1 interrupt not pending ack1 ?irq1 interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq1 latch. ack1 always reads as logic 0. reset clears ack1. imask1 ?irq1 interrupt mask bit writing a logic 1 to this read/write bit disables irq1 interrupt requests. reset clears imask1. 1 = irq1 interrupt requests disabled 0 = irq1 interrupt requests enabled address: $001e bit 7 654321 bit 0 read: 0000 irqf1 0 imask1 mode1 write: ack1 reset: 00000000 = unimplemented figure 12-3. irq status and control register (iscr)
external interrupt (irq) irq option control register MC68HC08JB1 ? rev. 1.0 technical data motorola external interrupt (irq) 183 mode1 ?irq1 edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode1. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only 12.9 irq option control register the irq option control register controls and monitors the external interrupt function available on the pte4 pin. it also disables/enables the pullup resistor on the irq pin. controls pullup option on irq pin enables pte4 pin for external interrupts to irq1 shows the state of the pte4 interrupt flag pte4if ?pte4 interrupt flag this read-only status bit is high when a falling edge on pte4 pin is detected. pte4if bit clears when the iocr is read. 1 = falling edge on pte4 is detected and pte4ie is set 0 = falling edge on pte4 is not detected or pte4ie is clear pte4ie ?pte4 interrupt enable this read/write bit enables or disables the interrupt function on the pte4 pin to trigger the irq1 interrupt. setting the pte4ie bit and clearing the usben bit in the usb address register configure the pte4 pin for interrupt function to the irq1 interrupt. setting pte4ie also enables the internal pullup on pte4 pin. address: $001c bit 7 654321 bit 0 read: 00000 pte4if pte4ie irqpd write: reset: 00000000 = unimplemented figure 12-4. irq option control register (iocr)
external interrupt (irq) technical data MC68HC08JB1 ? rev. 1.0 184 external interrupt (irq) motorola 1 = pte4 interrupt enabled; triggers irq1 interrupt 0 = pte4 interrupt disabled irqpd ?irq pullup disable this read/write bit controls the pull-up option for the irq pin. 1 = internal pull-up is disconnected 0 = internal pull-up is connected between irq pin and v dd
MC68HC08JB1 ? rev. 1.0 technical data motorola keyboard interrupt module (kbi) 185 technical data ?MC68HC08JB1 section 13. keyboard interrupt module (kbi) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 13.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 13.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 13.6 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.8 keyboard module during break interrupts . . . . . . . . . . . . . . . 191 13.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.9.1 keyboard status and control register. . . . . . . . . . . . . . . . 191 13.9.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 193 13.2 introduction the keyboard interrupt module (kbi) provides eight independently maskable external interrupts which are accessible via pta0?ta7 pins.
keyboard interrupt module (kbi) technical data MC68HC08JB1 ? rev. 1.0 186 keyboard interrupt module (kbi) motorola 13.3 features features of the keyboard interrupt module include: eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask hysteresis buffers programmable edge-only or edge- and level-interrupt sensitivity exit from low-power modes 13.4 pin name conventions the kbi share eight i/o pins with eight port a i/o pins. the full name of the i/o pins are listed in table 13-1 . the generic pin name appear in the text that follows. table 13-1. kbi pin name conventions full kbi pin names: kbi generic pin names: pta7/kba7 kba7 pta7/kba6 kba6 pta7/kba5 kba5 pta7/kba4 kba4 pta7/kba3 kba3 pta7/kba2 kba2 pta7/kba1 kba1 pta7/kba0 kba0
keyboard interrupt module (kbi) pin name conventions MC68HC08JB1 ? rev. 1.0 technical data motorola keyboard interrupt module (kbi) 187 figure 13-1. keyboard module block diagram kbie0 kbie7 . . . dq ck clr v reg modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kba7 kba0 synchronizer keyf keyboard interrupt request to pullup enable to pullup enable table 13-2. i/o register summary addr. register name bit 7 654321 bit 0 $0016 keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset: 00000000 $0017 keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset: 00000000 = unimplemented
keyboard interrupt module (kbi) technical data MC68HC08JB1 ? rev. 1.0 188 keyboard interrupt module (kbi) motorola 13.5 functional description writing to the kbie7?bie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pin. enabling a keyboard interrupt pin also enables its internal pullup device. a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. if the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. note: to prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. if the modek bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: vector fetch or software clear ?a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the interrupt acknowledge signal by writing a logic 1 to the ackk bit in the keyboard status and control register (kbscr). the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $fff0 and $fff1.
keyboard interrupt module (kbi) keyboard initialization MC68HC08JB1 ? rev. 1.0 technical data motorola keyboard interrupt module (kbi) 189 return of all enabled keyboard interrupt pins to logic 1 ?as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the keyboard interrupt pin is falling-edge- sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note: setting a keyboard interrupt enable bit (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a logic 0 for software to read the pin. 13.6 keyboard initialization when a keyboard interrupt pin is enabled, it takes time for the pullup device to reach a logic 1. therefore, a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register.
keyboard interrupt module (kbi) technical data MC68HC08JB1 ? rev. 1.0 190 keyboard interrupt module (kbi) motorola 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. an interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddra bits in data direction register a. 2. write logic 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 13.7 low-power modes the wait and stop instructions put the mcu in low-power consumption standby modes. 13.7.1 wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 13.7.2 stop mode the keyboard module remains active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode.
keyboard interrupt module (kbi) keyboard module during break interrupts MC68HC08JB1 ? rev. 1.0 technical data motorola keyboard interrupt module (kbi) 191 13.8 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. to allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break state has no effect. (see 13.9.1 keyboard status and control register .) 13.9 i/o registers these registers control and monitor operation of the keyboard module: keyboard status and control register (kbscr) keyboard interrupt enable register (kbier) 13.9.1 keyboard status and control register the keyboard status and control register: flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity
keyboard interrupt module (kbi) technical data MC68HC08JB1 ? rev. 1.0 192 keyboard interrupt module (kbi) motorola bits 7? ?not used these read-only bits always read as logic 0s. keyf ?keyboard flag bit this read-only bit is set when a keyboard interrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ?keyboard acknowledge bit writing a logic 1 to this write-only bit clears the keyboard interrupt request. ackk always reads as logic 0. reset clears ackk. imaskk ?keyboard interrupt mask bit writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ?keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only address: $0016 bit 7 654321 bit 0 read: 0000 keyf 0 imaskk modek write: ackk reset: 00000000 = unimplemented figure 13-2. keyboard status and control register (kbscr)
keyboard interrupt module (kbi) i/o registers MC68HC08JB1 ? rev. 1.0 technical data motorola keyboard interrupt module (kbi) 193 13.9.2 keyboard interrupt enable register the keyboard interrupt enable register enables or disables each port a pin to operate as a keyboard interrupt pin. kbie7?bie0 ?keyboard interrupt enable bits each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = ptax pin enabled as keyboard interrupt pin 0 = ptax pin not enabled as keyboard interrupt pin address: $0017 bit 7 654321 bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset: 00000000 figure 13-3. keyboard interrupt enable register (kbier)
keyboard interrupt module (kbi) technical data MC68HC08JB1 ? rev. 1.0 194 keyboard interrupt module (kbi) motorola
MC68HC08JB1 ? rev. 1.0 technical data motorola computer operating properly (cop) 195 technical data ?MC68HC08JB1 section 14. computer operating properly (cop) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.1 oscxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.4.8 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . 198 14.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.2 introduction the computer operating properly (cop) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in the config register.
computer operating properly (cop) technical data MC68HC08JB1 ? rev. 1.0 196 computer operating properly (cop) motorola 14.3 functional description figure 14-1 shows the structure of the cop module. figure 14-1. cop block diagram the cop counter is a free-running 6-bit counter preceded by a 12-bit system integration module (sim) counter. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ?2 4 or 2 13 ?2 4 oscxclk cycles, depending on the state of the cop rate select bit, coprs in the configuration register. with a 2 18 ?2 4 oscxclk cycle overflow option (coprs = 0), a 6mhz crystal gives a cop timeout period of 21.84 ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12 through 5 of the sim counter. copctl write oscxout reset vector fetch sim reset circuit reset status register internal reset sources (1) sim clear stages 5?2 12-bit sim counter clear all stages copd (from config) reset copctl write clear cop module copen (from sim) cop counter note: 1. see sim section for more details. cop clock cop timeout cop rate sel (coprs from config) 6-bit cop counter
computer operating properly (cop) i/o signals MC68HC08JB1 ? rev. 1.0 technical data motorola computer operating properly (cop) 197 note: service the cop immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 oscxclk cycles and sets the cop bit in the reset status register (rsr). note: place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt subroutine could keep the cop from generating a reset even while the main program is not working properly. 14.4 i/o signals the following paragraphs describe the signals shown in figure 14-1 . 14.4.1 oscxclk oscxclk is the clock doubler output signal. oscxclk frequency is double of the crystal frequency. 14.4.2 stop instruction the stop instruction clears the cop prescaler. 14.4.3 copctl write writing any value to the cop control register (copctl) (see 14.5 cop control register ) clears the cop counter and clears bits 12 through 5 of the sim counter. reading the cop control register returns the low byte of the reset vector. 14.4.4 power-on reset the power-on reset (por) circuit in the sim clears the cop prescaler 4096 oscxclk cycles after power-up.
computer operating properly (cop) technical data MC68HC08JB1 ? rev. 1.0 198 computer operating properly (cop) motorola 14.4.5 internal reset an internal reset clears the sim counter and the cop counter. 14.4.6 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the cop prescaler. 14.4.7 copd (cop disable) the copd signal reflects the state of the cop disable bit (copd) in the configuration register (config). 14.4.8 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the configuration register (config). coprs ?cop rate select bit coprs selects the cop timeout period. reset clears coprs. 1 = cop timeout period is (2 13 ?2 4 ) oscxout cycles 0 = cop timeout period is (2 18 ?2 4 ) oscxout cycles copd ?cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled address: $001f bit 7 654321 bit 0 read: 0 0 urstd lvid ssrec coprs stop copd write: reset: 00000000 = unimplemented figure 14-2. configuration register (config)
computer operating properly (cop) cop control register MC68HC08JB1 ? rev. 1.0 technical data motorola computer operating properly (cop) 199 14.5 cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 14.6 interrupts the cop does not generate cpu interrupt requests. 14.7 low-power modes the wait and stop instructions put the mcu in low-power consumption standby modes. 14.7.1 wait mode the cop remains active during wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. 14.7.2 stop mode stop mode turns off the oscxclk input to the cop and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. address: $ffff bit 7 654321 bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 14-3. cop control register (copctl)
computer operating properly (cop) technical data MC68HC08JB1 ? rev. 1.0 200 computer operating properly (cop) motorola the stop bit in the configuration register (config) enables the stop instruction. to prevent inadvertently turning off the cop with a stop instruction, disable the stop instruction by clearing the stop bit.
MC68HC08JB1 ? rev. 1.0 technical data motorola low voltage inhibit (lvi) 201 technical data ?MC68HC08JB1 section 15. low voltage inhibit (lvi) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 15.4 lvi control register (config) . . . . . . . . . . . . . . . . . . . . . . . 202 15.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 15.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 15.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 15.2 introduction this section describes the low-voltage inhibit module (lvi), which monitors the voltage on the v dd pin and generates a reset when the v dd voltage falls to the lvi trip (v lvr ) voltage. 15.3 functional description figure 15-1 shows the structure of the lvi module. the lvi is enabled after a reset. the lvi module contains a bandgap reference circuit and comparator. setting lvi disable bit (lvid) disables the lvi to monitor v dd voltage. the lvi module generates one output signal: lvi reset ?an reset signal will be generated to reset the cpu when v dd drops to below the set trip point.
low voltage inhibit (lvi) technical data MC68HC08JB1 ? rev. 1.0 202 low voltage inhibit (lvi) motorola figure 15-1. lvi module block diagram 15.4 lvi control register (config) lvid low voltage inhibit disable bit 1 = low voltage inhibit disabled 0 = low voltage inhibit enabled 15.5 low-power modes the stop and wait instructions put the mcu in low-power consumption standby modes. 15.5.1 wait mode the lvi module, when enabled, will continue to operate in wait mode. 15.5.2 stop mode the lvi module, when enabled, will continue to operate in stop mode. low v dd lvid detector v dd lvi reset v dd > v lvr = 0 v dd < v lvr = 1 address: $001f bit 7 654321 bit 0 read: 0 0 urstd lvid ssrec coprs stop copd write: reset: 00000000 one-time writable register after each reset. urstd and lvid bits are reset by por or lvi reset only. = unimplemented figure 15-2. configuration register (config)
MC68HC08JB1 ? rev. 1.0 technical data motorola electrical specifications 203 technical data ?MC68HC08JB1 section 16. electrical specifications 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 16.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 204 16.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.6 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 206 16.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.8 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.9 usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 208 16.10 usb low-speed source electrical characteristics . . . . . . . . 209 16.11 usb signaling levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.12 timer interface module characteristics . . . . . . . . . . . . . . . . . 210 16.2 introduction this section contains electrical and timing specifications.
electrical speci?ations technical data MC68HC08JB1 ? rev. 1.0 204 electrical specifications motorola 16.3 absolute maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. note: this device is not guaranteed to operate properly at the maximum ratings. refer to 16.6 dc electrical characteristics for guaranteed operating conditions. note: this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v reg . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v reg ). characteristic (1) notes: 1. voltages referenced to v ss symbol value unit supply voltage v dd ?.3 to +6.0 v input voltage pte4/d? pte3/d+ rst , irq , pta7 others v in v ss 1.0 to v dd +0.3 v ss 0.3 to v dd +0.3 v ss 0.3 to v reg +0.3 v mode entry voltage, irq pin v dd +v hi v ss 0.3 to +11 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg 55 to +150 c maximum current of ptd0/1 pin i ol 25 to +50 ma maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma
electrical specifications functional operating range MC68HC08JB1 ? rev. 1.0 technical data motorola electrical specifications 205 16.4 functional operating range 16.5 thermal characteristics characteristic symbol value unit operating temperature range t a 0 to 70 c operating voltage range v dd 4.0 to 5.5 v characteristic symbol value unit thermal resistance 20-pin pdip 20-pin soic q ja 70 70 c/w i/o pin power dissipation p i/o user-determined w power dissipation (1) notes: 1. power dissipation is a function of temperature. p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c ) + p d 2 q ja w/ c average junction temperature t j t a + (p d q ja ) c maximum junction temperature t jm 100 c
electrical speci?ations technical data MC68HC08JB1 ? rev. 1.0 206 electrical specifications motorola 16.6 dc electrical characteristics characteristic (1) notes: 1. v dd = 4.0 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min typ (2) 2. typical values reflect average measurements at midpoint of voltage range, 25 c only. max unit regulator output voltage v reg 3.0 3.3 3.6 v output high voltage (i load = 2.0 ma) pta0?ta7, ptc0, ptd0/1, pte1, pte3, pte4 v oh v reg 0.8 v output low voltage (i load = 1.6 ma) all i/o pins (i load = 50 ma) ptd0/1 in ildd mode (i load = 10 ma) pte4?te3 with usb disabled v ol 0.4 0.5 0.4 v input high voltage all ports, osc1 irq , rst v ih 0.7 v reg 0.7 v dd v reg v dd v input low voltage all ports, osc1 irq , rst v il v ss v ss 0.3 v reg 0.3 v dd v v dd supply current, v dd = 5.25v, f op = 3mhz run, with low speed usb (3) run, with usb suspended (3) wait, with low speed usb (4) wait, with usb suspended (4) stop (5) 0 c to 70 c i dd 2.5 2.2 2.2 2.0 300 5.5 5.0 4.5 4.0 350 ma ma ma ma m a i/o ports hi-z leakage current i il 10 m a input current i in 1 m a capacitance ports (as input or output) c out c in 12 8 pf por re-arm voltage (6) v por 0 100 mv por rise-time ramp rate (7) r por 0.035 v/ms monitor mode entry voltage v dd + v hi 1.4 v dd 8 v pullup resistors port a, port c, rst , irq pte4?te3 with usb module disabled d?with usb module enabled r pu 20 4 1.2 35 5 1.5 50 6 1.8 k w lvi reset v lv r 3.3 v lvi reset recover v lvrr 3.5 v ram data retention voltage v rdr 2.0 v
electrical specifications control timing MC68HC08JB1 ? rev. 1.0 technical data motorola electrical specifications 207 16.7 control timing 16.8 oscillator characteristics 3. run (operating) i dd measured using external square wave clock source (f xclk = 6 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f xclk = 6 mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; 15 k w 5% termination resistors on d+ and d?pins; all ports configured as inputs; osc2 capacitance linearly affects wait i dd 5. stop i dd measured with usb in suspend mode; osc1 grounded; transceiver pullup resistor of 1.5 k w 5% between v reg and d?and 15 k w 5% termination resistors on d+ and d?pins; no port pins sourcing current. 6. maximum is highest voltage that por is guaranteed. 7. if minimum v reg is not reached before the internal por reset is released, rst must be driven low externally until minimum v reg is reached. characteristic (1) notes: 1. v dd = 4.0 to 5.5 vdc; v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this in- formation. f op 3 mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 50 ns characteristic symbol min typ max unit crystal frequency (1) notes: 1. the usb module is designed to function at f xclk = 6 mhz. f xclk 1 6 mhz external clock reference frequency (1), (2) 2. no more than 10% duty cycle deviation from 50% f xclk dc 6 mhz crystal load capacitance (3) 3. consult crystal vendor data sheet c l crystal ?ed capacitance (3) c 1 2 c l crystal tuning capacitance (3) c 2 2 c l feedback bias resistor r b 10 m w series resistor (3), (4) 4. not required for high-frequency crystals r s
electrical speci?ations technical data MC68HC08JB1 ? rev. 1.0 208 electrical specifications motorola 16.9 usb dc electrical characteristics characteristic (1) notes: 1. v dd = 4.0 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol conditions min typ max unit hi-z state data line leakage i lo 0 v electrical specifications usb low-speed source electrical characteristics MC68HC08JB1 ? rev. 1.0 technical data motorola electrical specifications 209 16.10 usb low-speed source electrical characteristics characteristic (1) notes: 1. all voltages are measured from local ground, unless otherwise specified. all timings use a capacitive load of 50 pf, unless otherwise specified. low-speed timings have a 1.5k w pullup to 2.8 v on the d?data line. symbol conditions min typ max unit internal operating frequency f op ?mhz transition time (2) rise time fall time 2. transition times are measured from 10% to 90% of the data signal. the rising and falling edges should be smoothly tran- sitioning (monotonic). capacitive loading includes 50 pf of tester capacitance. t r t f c l = 200 pf c l = 600pf c l = 200 pf c l = 600pf 75 75 300 300 ns rise/fall time matching t rfm t r /t f 80 120 % low speed data rate t drate 1.5 mbs 1.5% 1.4775 676.8 1.500 666.0 1.5225 656.8 mbs ns source differential driver jitter to next transition for paired transitions t ddj1 t ddj2 c l = 600 pf measured at crossover point ?5 ?0 25 10 ns receiver data jitter tolerance to next transition for paired transitions t djr1 t djr2 c l = 600 pf measured at crossover point ?5 ?5 75 45 ns source seo interval of eop t leopt measured at crossover point 1.25 1.50 m s source jitter for differential transition to se0 transition (3) 3. the two transitions are a (nominal) bit time apart. measured at crossover point 667 ns receiver seo interval of eop must reject as eop must accept t leopr1 t leopr2 measured at crossover point 210 670 ns width of seo interval during differential transition t lst measured at crossover point 210 ns
electrical speci?ations technical data MC68HC08JB1 ? rev. 1.0 210 electrical specifications motorola 16.11 usb signaling levels 16.12 timer interface module characteristics bus state signaling levels transmit receive differential 1 d+ > v oh (min) and d?< v ol (max) (d+) ?(d? > 200 mv differential 0 d?> v oh (min) and d?< v ol (max) (d? ?(d+) > 200 mv single-ended 0 (se0) d+ and d?< v ol (max) d+ and d?< v il (max) data j state (low speed) differential 0 differential 0 data k state (low speed) differential 1 differential 1 idle state (low speed) na d?> v ihz (min) and d+ < v il (max) resume state differential 1 differential 1 start of packet (sop) data lines switch from idle to k state end of packet (eop) se0 for approximately 2 bit times (1) followed by a j state for 1 bit time notes: 1. the width of eop is defined in bit times relative to the speed of transmission. se0 for 3 1 bit time (2) followed by a j state for 1 bit time 2. the width of eop is defined in bit times relative to the device type receiving the eop. the bit time is approximate. reset na d+ and d?< v il (max) for 3 8 m s characteristic symbol min max unit input capture pulse width t tih, t til 125 ns input clock pulse width t tch, t tcl (1/f op ) + 5 ?s
MC68HC08JB1 ? rev. 1.0 technical data motorola mechanical specifications 211 technical data ?MC68HC08JB1 section 17. mechanical specifications 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 17.3 20-pin dual in-line package (pdip) . . . . . . . . . . . . . . . . . . . 212 17.4 20-pin small outline integrated circuit (soic) . . . . . . . . . . . 212 17.2 introduction this section gives the dimensions for: 20-pin plastic dual in-line package (case 738) 20-pin small outline integrated circuit package (case 751d) the following figures show the latest package drawing at the time of this publication. to make sure that you have the latest package specifications, contact one of the following: local motorola sales office world wide web at http://www.motorola.com/semiconductors/ follow the world wide web on-line instructions to retrieve the current mechanical specifications.
mechanical speci?ations technical data MC68HC08JB1 ? rev. 1.0 212 mechanical specifications motorola 17.3 20-pin dual in-line package (pdip) figure 17-1. 20-pin pdip (case #738) 17.4 20-pin small outline integrated circuit (soic) figure 17-2. 20-pin soic (case #751d) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 a seating plane k n f g d 20 pl t m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c t seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029

mc68hc08 jb 1 /d rev 1 mc 68hc08a s60 t echnical data how to reach us: usa/europe/loc a tions not listed: motorola literature distribution p .o. box 5405 denve r , colorado 80217 1-303-675-2140 1-800-441-2447 technica l inform a tion center: 1-800-521-6274 ja p an: motorola japan ltd. sps , t echnical information center 3-20-1, minami-azabu, minato-ku t okyo 106-8573 japan 81-3-3440-3569 asia/ p acific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street t ai po industrial estate t ai po, n. t ., hong kong 852-26668334 home p age: http://ww w .motorola.com/semiconductors/ q4/00 rev 1

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